DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 377

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14 PIN ASSIGNMENT
Table 14-1
Table 14-1. Pin Assignment Breakdown
I/O Signals
Digital VDD
Analog VDD
VSS
Total
Figure 14-1. DS3184 Pin Assignments—400-Lead TE-PBGA
Note: Green indicates VSS, Red indicates VDD, and Yellow indicates system interface pins.
W
M
G
B
C
D
H
K
N
R
U
A
E
P
V
Y
F
L
T
J
VDD_RX1
VDD_RX2
VDD_JA1
VDD_TX2
GPIO[5]
GPIO[7]
MODE
RXN1
TXN1
CLKA
CLKB
TXN2
RXN2
VDD
VSS
D[0]
D[1]
VSS
A[1]
A[0]
1
ROHSOF
ROHSOF
GPIO[6]
GPIO[8]
details the breakdown of the assigned pins for each device.
RXP1
CLKC
RXP2
TXP1
RDY*
TXP2
VDD
ALE
D[2]
D[3]
D[4]
D[5]
A[5]
A[4]
A[3]
A[2]
2
1
2
396 assigned
RPOS1 VDD_RX3
RNEG1
RNEG2
RPOS2 VDD_RX4
JTCLK
TEST*
A[10]
D[10]
JTDI
D[6]
D[7]
HIZ*
D[8]
D[9]
A[9]
A[8]
A[7]
A[6]
RD*
CS*
3
DS3184
pins
275
VDD_TX1
UNUSED
UNUSED
40
13
68
JTRST*
TCLKI1
TPOS1
TNEG1
TNEG2
TPOS2
TCLKI2
JTMS
JTDO
D[11]
D[12]
D[13]
D[14]
WR*
INT*
4
1
2
VDD_CLA
TPDENI1 VDD_JA3
UNUSED
UNUSED
VDD_JA2
TPDENI2 VDD_JA4
ROHCLK
TOHEN1
TOHEN2
ROHCLK
GPIO[1]
GPIO[2]
GPIO[4]
GPIO[3]
WIDTH
RXN3
RXP3
RXP4
RXN4
D[15]
5
D
1
3
4
2
366 assigned
RPDENI1 TCLKO1
RPDENI2 TCLKO2
TSER1 VDD_TX3 RSOFO1
TSER2 VDD_TX4 RSOFO2
TXN3
TXP3
TXP4
TXN4
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
6
DS3183
pins
245
40
13
68
TSOFO1 TLCLK1
TOHSOF
TOHSOF
TSOFO2 TLCLK2
TSOFI1
TSOFI2
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VDD
VDD
VDD
7
1
2
TOHCLK1 RPDAT1 TPDAT3
TOHCLK2 RPDAT2 TPDAT4
RLCLK1
RLCLK2
TOH1
TOH2
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VDD
VDD
VDD
8
336 assigned
TPDENO
TPDENO
TPDAT1
RCLKO1
RCLKO2
TPDAT2
RSER1
RSER2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
9
1
2
DS3182
pins
215
40
13
68
TPDENO
TPDENO
RPDAT3 RCLKO3 RLCLK3 TCLKO3
RPDAT4 RCLKO4 RLCLK4 TCLKO4
ROH1
ROH3
ROH4
ROH2
377
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
10
3
4
TOHCLK3
TOHCLK4
TLCLK3 TSOFO3
TLCLK4 TSOFO4
RSER3
RSER4
TOH3
TOH4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
11
306 assigned
RSOFO3 RPDENI3 TNEG3
TOHSOF
TOHSOF
RSOFO4 RPDENI4 TNEG4
TSOFI3 TPDENI3
TSOFI4 TPDENI4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
12
DS3181
3
4
pins
185
40
13
68
ROHCLK
ROHCLK
TSER3
TSER4
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VDD
VDD
VDD
13
3
4
ROHSOF
ROHSOF
TOHEN3 TADR[2]
TOHEN4
TCLKI3
TCLKI4
TPOS3
TPOS4
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VDD
VDD
VDD
14
3
4
TDATA[30
TDATA[31
TADR[4]
TADR[3]
RNEG3
RNEG4
RPOS3
RPOS4
TEOP
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VDD
VDD
VDD
15
]
]
TDATA[21
TDATA[22
TDATA[23
TDATA[17
TDATA[29
TDATA[15
RDATA[3
RDATA[3
RDATA[2
RDATA[2
RDATA[1
RDATA[1
RDATA[1
RDATA[1
TADR[1]
REOP
TSOX
TSPA
RST*
16
TSX
1]
0]
9]
8]
5]
4]
3]
2]
]
]
]
]
]
]
TDATA[19
TDATA[26
TDATA[16
TDATA[18
TDATA[28
TDATA[12
TDATA[14
RDATA[9] RDATA[8] RDATA[7] RDATA[6]
RDATA[2
RDATA[2
RDATA[2
RDATA[2
RDATA[2
RDATA[1
RDATA[1
TMOD[0] TMOD[1] TDATA[9]
TDXA[1]
TPRTY
RSOX
TERR
17
7]
6]
5]
4]
3]
1]
0]
]
]
]
]
]
]
]
TDATA[20
TDATA[27
TDATA[11
TDATA[13
RDATA[2] RDATA[1] RSCLK
RDATA[5] RDATA[4] RDATA[3]
TDATA[1] RADR[4] RADR[3]
TDATA[6] TDATA[3] TDATA[0]
TDATA[5] TDATA[4] TDATA[2]
RDATA[2
RDATA[2
RDATA[2
RMOD[0] RMOD[1] RDATA[0]
RDXA[3] RDXA[2]
RADR[2] RADR[1] RADR[0]
TADR[0]
REN*
RVAL
18
0]
2]
1]
]
]
]
]
TDATA[25
TDATA[10
RDATA[1
RDATA[1
RDXA[1]
TDXA[4]
TDXA[3] RDXA[4]
RERR
TEN*
VDD
19
9]
8]
]
]
TDATA[24
TDATA[8]
TDATA[7]
RDATA[1
RDATA[1
TDXA[2]
TSCLK
RPRTY
VDD
20
VSS
VSS
7]
6]
]