DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 365

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 7: Receive FCS Errored Packet Interrupt Enable (REPIE) – This bit enables an interrupt if the REPL bit in the
PP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 6: Receive Aborted Packet Interrupt Enable (RAPIE) – This bit enables an interrupt if the RAPL bit in the
PP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 5: Receive Invalid Packet Detected Interrupt Enable (RIPDIE) – This bit enables an interrupt if the RIPDL bit
in the PP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 4: Receive Small Packet Detected Interrupt Enable (RSPDIE) – This bit enables an interrupt if the RSPDL bit
in the PP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 3: Receive Large Packet Detected Interrupt Enable (RLPDIE) – This bit enables an interrupt if the RLPDL bit
in the PP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 2: Receive FCS Errored Packet Count Interrupt Enable (REPCIE) – This bit enables an interrupt if the
REPCL bit in the PP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Must be set low when the packets do not have a FCS appended.
Bit 1: Receive Aborted Packet Count Interrupt Enable (RAPCIE) – This bit enables an interrupt if the RAPCL bit
in the PP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 0: Receive Size Violation Packet Count Interrupt Enable (RSPCIE) – This bit enables an interrupt if the
RSPCL bit in the PP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
REPIE
15
—
0
7
0
RAPIE
14
—
0
6
0
PP.RSRIE
Packet Processor Receive Status Register Interrupt Enable
(1,3,5,7)D2h
RIPDIE
13
—
0
5
0
RSPDIE
12
—
0
0
4
365
Reserved
RLPDIE
11
0
3
0
Reserved
REPCIE
10
0
2
0
Reserved
RAPCIE
9
0
1
0
Reserved
RSPCIE
8
0
0
0