DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 198

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.16.3 Detailed Description
The receiver performs clock and data recovery from an alternate mark inversion (AMI) coded signal or a B3ZS- or
HDB3-coded AMI signal and monitors for loss of the incoming signal. The transmitter drives standard pulse-shape
waveforms onto 75Ω coaxial cable. See
LIU. The jitter attenuator can be mapped into the receiver data path, mapped into the transmitter data path, or be
disabled. The DS3/E3/STS1 LIU conforms to the telecommunications standards listed in
shows the external components required for proper operation.
Figure 10-58. DS3/E3/STS-1 LIU Block Diagram
10.16.4 Transmitter
10.16.4.1 Transmit Clock
The clock used in the LIU Transmitter is typically based on either the CLAD clock or TCLKI, selected by the
CLADC bit in PORT.CR3.
10.16.4.2 Waveshaping, Line Build-Out, Line Driver
The waveshaping block converts the transmit clock, positive data, and negative data signals into a single AMI
signal with the waveshape required for interfacing to DS3/E3/STS1 lines.
Figure 18-9
Because DS3 and STS-1 signals must meet the waveform templates at the cross-connect through any cable length
from 0 to 450ft, the waveshaping circuitry includes a selectable LBO feature. For cable lengths of 225ft or greater,
the TLBO configuration bit (PORT.CR2.TLBO) should be low. When TLBO is low, output pulses are driven onto the
coaxial cable without any pre-attenuation. For cable lengths less than 225ft, TLBO should be high to enable the
LBO circuitry. When TLBO is high, pulses are pre-attenuated by the LBO circuitry before being driven onto the
coaxial cable. The LBO circuitry provides attenuation that mimics the attenuation of 225ft of coaxial cable.
The transmitter line driver can be disabled and the TXPn and TXNn outputs tri-stated by asserting the LTS
configuration bit (PORT.CR2.LTS). Powering down the transmitter through the TPD configuration bit (CPU bus
mode) also tri-states the TXPn and TXNn outputs.
TO DS3/E3/STS-1
FROM DS3/E3/
STS-1 LINE
LINE
(AC Timing Section) show the waveform template specifications and test parameters.
TXPn
TXNn
RXPn
RXNn
VDD
VSS
Supply
Power
Analog
Local
Loopback
Monitor
Driver
CLKA
Automatic
Equalizer
Adaptive
Control
Clock Rate
Gain
Adapter
+
ALOS
Figure 10-58
CLKB
squelch
CLKC
Recovery
Clock &
Data
for a detailed functional block diagram of the DS3/E3/STS-1
198
Table 18-8
TO B3ZS/HDB3
FROM B3ZS/HDB3
DECODER
ENCODER
through
Table
Table 18-12
4-1.
Figure 1-1
and