DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 338

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.14 Cell/Packet Processor
12.14.1 Transmit Cell Processor Register Map
The transmit cell processor block has 11 registers. Note: These registers are shared with the transmit packet
processors.
Table 12-47. Transmit Cell Processor Register Map
12.14.1.1 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 11: Transmit DSS Scrambling Enable (TDSE) – When 0, self-synchronous scrambling is enabled. When 1,
DSS scrambling is enabled DSS mode is only applicable for un-framed or clear channel framing and bit
synchronous modes. This bit is ignored if scrambling is disabled. Note: In byte synchronous and cell pass-through
modes, self-synchronous scrambling is enabled regardless of the setting of this bit.
Bit 10: Transmit DQDB HEC Processing Enable (TDHE) – When 0, the HEC is calculated over all four-header
bytes. When 1, only the last three header bytes are used for HEC calculation.
Bit 9: Transmit HEC Pass-through Enable (THPE) – When 0, the calculated HEC byte will overwrite the HEC
byte in the cell. When 1, the HEC byte in the cell is passed through. Note: The calculated HEC is always inserted
into cells that are received without a HEC byte.
Bit 8: Transmit HEC Coset Polynomial Addition Disable (TCPAD) – When 0, the HEC coset polynomial
addition is performed prior to inserting the HEC byte. When 1, HEC coset polynomial addition is disabled
(1,3,5,7)ACh
(1,3,5,7)BCh
(1,3,5,7)AAh
(1,3,5,7)AEh
(1,3,5,7)BAh
(1,3,5,7)BEh
(1,3,5,7)A0h
(1,3,5,7)A2h
(1,3,5,7)A4h
(1,3,5,7)A6h
(1,3,5,7)A8h
(1,3,5,7)B0h
(1,3,5,7)B2h
(1,3,5,7)B4h
(1,3,5,7)B6h
(1,3,5,7)B8h
ADDRESS
15
—
—
0
7
0
CP.THMRC
REGISTER
CP.TCCR1
CP.TCCR2
CP.THPC1
CP.THPC2
CP.TFPPC
CP.TSRIE
CP.TECC
CP.TSRL
CP.TCR
CP.TSR
—
—
—
—
—
14
—
—
0
6
0
Cell Processor Transmit Control Register
Reserved
Cell Processor Transmit Errored Cell Control Register
Cell Processor Transmit HEC Error Mask Control Register
Cell Processor Transmit Header Pattern Control Register 1
Cell Processor Transmit Header Pattern Control Register 2
Cell Processor Transmit Fill Cell Payload Pattern Control Register
Cell Processor Transmit Status Register
Cell Processor Transmit Status Register Latched
Cell Processor Transmit Status Register Interrupt Enable
Cell Processor Transmit Cell Count Register 1
Cell Processor Transmit Cell Count Register 2
Reserved
Reserved
Unused
Unused
CP.TCR
Cell Processor Transmit Control Register
(1,3,5,7)A0h
TFCH
13
—
0
5
0
REGISTER DESCRIPTION
TFCP
12
—
0
0
4
338
TDSE
THSE
11
0
3
0
TDHE
TSD
10
0
2
0
THPE
TBRE
9
0
1
0
TCPAD
TCPD
8
0
0
0