DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 244

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 12 to 8: Pattern Tap Feedback (PTF[4:0]) – These five bits control the PRBS “tap” feedback of the pattern
generator. The “tap” feedback will be from bit y of the pattern generator (y = PTF[4:0] +1). These bits are ignored
when programmed for a repetitive pattern. For a PRBS signal, the feedback is an XOR of bit n and bit y.
Bit 6: QRSS Enable (QRSS) – When 0, the pattern generator configuration is controlled by PTS, PLF[4:0], and
PTF[4:0], and BSP[31:0]. When 1, the pattern generator configuration is forced to a PRBS pattern with a
generating polynomial of x
bits are all zero.
Bit 5: Pattern Type Select (PTS) – When 0, the pattern is a PRBS pattern. When 1, the pattern is a repetitive
pattern.
Bits 4 to 0: Pattern Length Feedback (PLF[4:0]) – These five bits control the “length” feedback of the pattern
generator. The “length” feedback will be from bit n of the pattern generator (n = PLF[4:0] +1). For a PRBS signal,
the feedback is an XOR of bit n and bit y. For a repetitive pattern the feedback is bit n.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 0: BERT Seed/Pattern (BSP[15:0]) – Lower 16 bits of 32 bits. Register description follows next register.
BSP15
BSP7
15
15
—
—
0
7
0
0
7
0
BSP14
QRSS
20
BSP6
14
14
—
+ x
0
6
0
0
6
0
17
BERT.PCR
BERT Pattern Configuration Register
(0,2,4,6)62h
BERT.SPR1
BERT Seed/Pattern Register 1
(0,2,4,6)64h
+ 1. The output of the pattern generator will be forced to one if the next 14 output
BSP13
BSP5
PTS
13
13
—
0
5
0
0
5
0
BSP12
BSP4
PTF4
PLF4
12
12
0
0
0
0
4
4
244
BSP11
BSP3
PTF3
PLF3
11
11
0
3
0
0
3
0
BSP10
BSP2
PTF2
PLF2
10
10
0
2
0
0
2
0
BSP9
BSP1
PTF1
PLF1
9
0
1
0
9
0
1
0
BSP8
BSP0
PTF0
PLF0
8
0
0
0
8
0
0
0