DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 135

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.6.6 System Interface Bus Controller
The Transmit and Receive System Interface Bus Controller can be programmed to operate as a UTOPIA Level 2,
UTOPIA Level 3, POS-PHY Level 2, or POS-PHY Level 3 (or SPI-3) bus controller. It controls the system interface
bus timing and provides a common interface to the Transmit and Receive FIFO for FIFO status polling and
cell/packet data transfer. Normally, the first byte transmitted is transferred across the system interface as the most
significant byte (TDATA[31:24] in 32-bit mode or TDATA[15:8] in 16-bit mode). If byte reordering is enabled, the
first byte transmitted is transferred across the system interface as the least significant byte (TDATA[7:0]).On the
receive side, the first byte received is transferred across the system interface as the most significant byte
(RDATA[31:24] in 32-bit mode or RDATA[15:8] in 16-bit mode). If byte reordering is enabled, the first byte received
is transferred across the system interface as the least significant byte (RDATA[7:0]).
See
Figure 10-21. Normal Packet Format in 32-Bit Mode
Bit 31
Figure 10-22. Normal Packet Format in 16-Bit Mode
Bit 15
Figure 10-23. Byte Reordered Packet Format in 32-Bit Mode
Bit 31
Byte 4n-7
Byte 4n-3
Byte 2n-3
Byte 2n-1
Byte 4n-4
Byte 4n
Byte 1
Byte 5
Byte 1
Byte 3
Byte 4
Byte 8
Figure
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10-21,
Byte 4n-6
Byte 4n-2
Byte 2n-2
Byte 4n-5
Byte 4n-1
Figure
Byte 2n
Byte 2
Byte 6
Byte 2
Byte 4
Byte 3
Byte 7
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Bit 0
10-22,
Figure
Byte 4n-5
Byte 4n-1
Byte 4n-6
Byte 4n-2
(n-1)
Byte 3
Byte 7
Byte 2
Byte 6
2
n
1
nd
st
th
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10-23, and
th
Transfer
Transfer
Transfer
Transfer
Byte 4n-4
Byte 4n-7
Byte 4n-3
Figure 10-24.
Byte 4n
Byte 4
Byte 8
Byte 1
Byte 5
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135
Bit 0
Bit 0
Byte reordering is ignored in 8-bit mode.
(n-1)
(n-1)
2
2
n
n
1
1
nd
nd
st
th
st
th
th
th
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
DS3181/DS3182/DS3183/DS3184