DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 11

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS3181/DS3182/DS3183/DS3184
LIST OF TABLES
Table 4-1. Standards Compliance ............................................................................................................................. 23
Table 6-1. DS3/E3 ATM/Packet Mode Configuration Registers................................................................................ 26
Table 6-2. DS3/E3 ATM/Packet—OHM Mode Configuration Registers.................................................................... 27
Table 6-3. DS3/E3 Internal Fractional (IFRAC) ATM/Packet Mode Configuration Registers ................................... 28
Table 6-4. DS3/E3 External Fractional (XFRAC) ATM/Packet Mode Configuration Registers................................. 29
Table 6-5. DS3/E3 Flexible External Fractional (Subrate) Mode Configuration Registers........................................ 30
Table 6-6. DS3/E3 G.751 PLCP ATM Mode Configuration Registers ...................................................................... 31
Table 6-7. DS3/E3 G.751 PLCP ATM—OHM Mode Configuration Registers .......................................................... 32
Table 6-8. Clear-Channel ATM/Packet Mode Configuration Modes ......................................................................... 34
Table 6-9. Clear-Channel ATM/Packet—OHM Mode Configuration Registers......................................................... 35
Table 6-10. Clear-Channel Octet Aligned ATM/Packet—OHM Mode Configuration Registers................................ 36
Table 7-1. HDB3/B3ZS/AMI LIU Mode Configuration Registers ............................................................................... 37
Table 7-2. HDB3/B3ZS/AMI Non-LIU Mode Configuration Registers ....................................................................... 39
Table 7-3. UNI Line Interface Mode Configuration Registers.................................................................................... 40
Table 7-4. UNI Line Interface—OHM Mode Configuration Registers........................................................................ 41
Table 8-1. DS3184 Short Pin Descriptions................................................................................................................ 42
Table 8-2. Detailed Pin Descriptions ......................................................................................................................... 48
Table 9-1. Configuration of Global Register Settings ................................................................................................ 93
Table 9-2. Configuration of Port Register Settings .................................................................................................... 93
Table 10-1. LIU Enable Table.................................................................................................................................. 100
Table 10-2. All Possible Clock Sources Based on Mode and Loopback................................................................. 100
Table 10-3. Source Selection of TLCLK Clock Signal ............................................................................................. 101
Table 10-4. Source Selection of TCLKOn (internal TX clock) ................................................................................. 102
Table 10-5. Source Selection of RCLKO Clock Signal (internal RX clock) ............................................................. 102
Table 10-6. Transmit Line Interface Signal Pin Valid Timing Source Select ........................................................... 103
Table 10-7. Transmit Framer Pin Signal Timing Source Select .............................................................................. 104
Table 10-8. Receive Line Interface Pin Signal Timing Source Select ..................................................................... 104
Table 10-9. Receive Framer Pin Signal Timing Source Select ............................................................................... 105
Table 10-10. Reset and Power-Down Sources ....................................................................................................... 108
Table 10-11. CLAD IO Pin Decode.......................................................................................................................... 111
Table 10-12. Global 8 kHz Reference Source Table............................................................................................... 112
Table 10-13. Port 8 kHz Reference Source Table................................................................................................... 112
Table 10-14. GPIO Global Signals .......................................................................................................................... 113
Table 10-15. GPIO Pin Global Mode Select Bits..................................................................................................... 113
Table 10-16. GPIO Port Alarm Monitor Select ........................................................................................................ 114
Table 10-17. Loopback Mode Selections ................................................................................................................ 116
Table 10-18. Line AIS Enable Modes ...................................................................................................................... 120
Table 10-19. Payload (Downstream) AIS Enable Modes ........................................................................................ 121
Table 10-20. TSOFIn/TOHMIn Input Pin Functions ................................................................................................ 122
Table 10-21. TSERn/TPOHn/TFOHn Input Pin Functions ...................................................................................... 122
Table 10-22. TPDENIn/TPOHENn/TFOHENIn Input Pin Functions ....................................................................... 123
Table 10-23. TSOFOn/TDENn/TPOHSOFn/TFOHENOn Output Pin Functions .................................................... 123
Table 10-24. TCLKOn/TGCLKn/TPOHCLKn Output Pin Functions........................................................................ 124
Table 10-25. TPDATn Input Pin Functions.............................................................................................................. 124
Table 10-26. TPDENOn Output Pin Functions........................................................................................................ 124
Table 10-27. RSERn/RPOHn Output Pin Functions ............................................................................................... 125
Table 10-28. RPDENIn/RFOHENIn Input Pin Functions......................................................................................... 125
Table 10-29. RPDATn Input Pin Functions ............................................................................................................. 125
Table 10-30. RSOFOn/RDENn/RPOHSOFn/RFOHENOn Output Pin Functions................................................... 126
Table 10-31. RCLKOn/RGCLKn/RPOHCLKn Output Pin Functions ...................................................................... 126
Table 10-32. Framing Mode Select Bits FM[5:0] ..................................................................................................... 127
Table 10-33. Line Mode Select Bits LM[2:0]............................................................................................................ 133
Table 10-34. C-Bit DS3 Frame Overhead Bit Definitions ........................................................................................ 169
Table 10-35. M23 DS3 Frame Overhead Bit Definitions ......................................................................................... 171
Table 10-36. G.832 E3 Frame Overhead Bit Definitions ......................................................................................... 177
Table 10-37. Payload Label Match Status............................................................................................................... 180
Table 10-38. Pseudorandom Pattern Generation.................................................................................................... 194
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