DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 77

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 8-27. UTOPIA Level 2 Transmit Multiple Cell Transfer Polled Mode
Figure 8-28
2, the ATM device polls PHY device 'N'. On clock edge 3, PHY device 'N' indicates to the ATM device that it has a
complete cell ready for transfer by asserting RPXA. On clock edge 4, the ATM device selects PHY device 'N'. On
clock edge 5, the ATM device asserts REN. On clock edge 6, PHY device 'N' starts a cell transfer by placing the
first byte of cell data on RDATA, and asserting RSOX to indicate the transfer of the first byte of the cell. On clock
edge 7, PHY device 'N' deasserts RSOX as it continues to place additional bytes of the cell on RDATA. On clock
edge 12, the ATM device polls PHY device 'O'. On clock edge 13, PHY device 'O' indicates to the ATM device that
it has a complete cell ready for transfer by asserting RPXA. On clock edge 16, the ATM device deselects PHY
device 'N' and selects PHY device 'O' by deasserting REN and placing PHY device 'O's address on RADR. On
clock edge 17, the ATM device asserts REN and PHY device 'N' stops transferring cell data and tri-states its
RDATA and RSOX outputs. On clock edge 18, PHY device 'O' starts a cell transfer by placing the first byte of cell
data on RDATA, and asserting RSOX to indicate the transfer of the first byte of the cell. On clock edge 19, PHY
device 'O' deasserts RSOX as it continues to place additional bytes of the cell on RDATA.
Figure 8-28. UTOPIA Level 2 Receive Multiple Cell Transfer Polled Mode
Figure 8-29
transfer was started. On clock edge 4, since no other PHY device has a cell ready for transfer, the ATM device
assumes another cell transfer from PHY device 'N' and leaves REN asserted. On clock edge 5, PHY device 'N'
stops transferring cell data and indicates that it does not have another cell ready for transfer by not asserting
RSOX. On clock edge 6, the ATM device deasserts REN to end the cell transfer process. At the same time, PHY
device 'N' indicates to the ATM device that it now has a complete cell ready for transfer by placing the first byte of
cell data on RDAT, and asserting RSOX to indicate the transfer of the first byte of the cell. On clock edge 7, PHY
device 'N' tri-states its RDAT and RSOX outputs because REN is deasserted. On clock edge 8, the ATM device
selects PHY device 'N'. On clock edge 9, the ATM device asserts REN. On clock edge 10, PHY device 'N'
continues the cell transfer by placing the second byte of cell data on RDAT, and deasserting RSOX.
Cell From:
RDATA
Transfer
RSOX
TDATA
RADR
RCLK
RPXA
TADR
TSOX
TCLK
TPXA
TEN
REN
Transfer
Cell To:
shows a multidevice receive-interface multiple cell transfer from different PHY devices. On clock edge
shows a multidevice receive-interface unexpected multiple cell transfer. Prior to clock edge 1, the cell
M
M
1
1
M
1F
1F
M
2
2
N
N
3
3
1F
N
1F
N
4
4
N
N
5
5
H1
N
1F
1F
N
6
6
H2
H1
O
O
7
7
H3
H2
1F
1F
O
O
8
…
…
8
…
…
P42
9
9
P41
1F
1F
P
L
77
10
10
P43 P44 P45 P46 P47 P48
N
P42
L
M
11
11
N
P43 P44 P45 P46 P47 P48
1F
M
L
1F M
12
12
O
13
13
M
1F
1F
O
14
14
N
P
15
15
1F
N
1F
P
16
16
O
O
17
17
H1
1F
O
O
1F P
18
18
H2
H1
N
O
19
19
H3
O
H2
1F
1F
P
N
20
20
H4
H3
L
P