UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 124

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Notes
Address
FFF9CH
FFF9DH
FFFAAH
FFFABH
FFF9AH
FFF9BH
FFF9EH
FFF9FH
FFFA0H
FFFA1H
FFFA2H
FFFA3H
FFFA4H
FFFA5H
FFFA6H
FFFA8H
FFFA9H
FFFB0H
FFFB1H
FFF90H
FFF91H
FFF92H
FFF93H
FFF94H
FFF95H
FFF96H
FFF97H
FFF98H
FFF99H
122
Sub-count register
Second count register
Minute count register
Hour count register
Week count register
Day count register
Month count register
Year count register
Watch error correction register
Alarm minute register
Alarm hour register
Alarm week register
Real-time counter control register 0
Real-time counter control register 1
Real-time counter control register 2
Real-time counter control register 0
Real-time counter control register 1
Real-time counter control register 2
Clock operation mode control
register
Clock operation status control
register
Oscillation stabilization time counter
status register 0
Oscillation stabilization time counter
status register 1
Reset control flag register
Low-voltage detection register
Low-voltage detection level select
register
Watchdog timer enable register
DMA SFR address register 0
DMA SFR address register 1
1.
2.
3.
4.
5.
Special Function Register (SFR)
The value of this register is 00H if the AMPM bit (bit 3 of the RTCC0 register) is set to 1 after reset.
The reset value of RESF varies depending on the reset source.
The reset value of LVIM varies depending on the reset source and the setting of the option byte.
The reset value of LVIS varies depending on the reset source.
The reset value of WDTE is determined by the setting of the option byte.
Name
RSUBC
SEC
MIN
HOUR
WEEK
DAY
MONTH
YEAR
SUBCUD
ALARMWM
ALARMWH
ALARMWW
RTCC0
RTCC1
RTCC2
CMC
CSC
OSTC
OSTS
CKC
CKS0
CKS1
RESF
LVIM
LVIS
WDTE
DSA0
DSA1
CHAPTER 3 CPU ARCHITECTURE
Symbol
Table 3-5. SFR List (3/5)
User’s Manual U19678EJ1V1UD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
Manipulable Bit Range
1-bit
−
−
−
−
−
−
−
−
−
−
−
−
√
√
√
−
√
√
−
√
√
√
−
√
√
−
−
−
8-bit
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
16-bit
√
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1A/9A
12H
0EH
00H
00H
0000H
Reset
After
C0H
00H
00H
00H
01H
01H
00H
00H
00H
12H
00H
00H
00H
00H
00H
00H
07H
09H
00H
00H
00H
00H
Note 2
Note 3
Note 1
Note 4
Note 5
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
√
√
√
√
√
−
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√