UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 777

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Symbol
Address: FFF52H
IICF
Note Bits 6 and 7 are read-only.
Cautions 1. Write to STCEN only when the operation is stopped (IICE = 0).
Remark
Condition for clearing (IICRSV = 0)
• Cleared by instruction
• Reset
Condition for clearing (STCEN = 0)
• Cleared by instruction
• Detection of start condition
• Reset
Condition for clearing (STCF = 0)
• Cleared by STT = 1
• When IICE = 0 (operation stop)
• Reset
Condition for clearing (IICBSY = 0)
• Detection of stop condition
• When IICE = 0 (operation stop)
• Reset
IICBSY
STCEN
IICRSV
STCF
STCF
<7>
0
1
0
1
0
1
0
1
Generate start condition
Start condition generation unsuccessful: clear STT flag
Bus release status (communication initial status when STCEN = 1)
Bus communication status (communication initial status when STCEN = 0)
Enable communication reservation
Disable communication reservation
After operation is enabled (IICE = 1), enable generation of a start condition upon detection of
a stop condition.
After operation is enabled (IICE = 1), enable generation of a start condition without detecting
a stop condition.
2. As the bus release status (IICBSY = 0) is recognized regardless of the actual bus
3. Write to IICRSV only when the operation is stopped (IICE = 0).
STT: Bit 1 of IICA control register 0 (IICCTL0)
IICE: Bit 7 of IICA control register 0 (IICCTL0)
IICBSY
<6>
After reset: 00H
status when STCEN = 1, when generating the first start condition (STT = 1), it is
necessary to verify that no third party communications are in progress in order to
prevent such communications from being destroyed.
Figure 14-8. Format of IICA Flag Register (IICF)
5
0
CHAPTER 14 SERIAL INTERFACE IICA
User’s Manual U19678EJ1V1UD
R/W
Communication reservation function disable bit
4
0
Note
3
0
Initial start enable trigger
I
2
C bus status flag
STT clear flag
Condition for setting (IICRSV = 1)
• Set by instruction
Condition for setting (STCF = 1)
• Generating start condition unsuccessful and STT
Condition for setting (IICBSY = 1)
• Detection of start condition
• Setting of IICE when STCEN = 0
Condition for setting (STCEN = 1)
• Set by instruction
2
0
cleared to 0 when communication reservation is
disabled (IICRSV = 1).
STCEN
<1>
IICRSV
<0>
775