UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 359

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UPD78F1233GB-GAH-AX

Manufacturer Part Number
UPD78F1233GB-GAH-AX
Description
MCU 16BIT 78K0R/LX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet

Specifications of UPD78F1233GB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1233GB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
TOM0
TMRp
TMRq
TOE0
TOL0
Remark
TO0
(a) Timer mode register p, q (TMRp, TMRq)
(b) Timer output register 0 (TO0)
(c) Timer output enable register 0 (TOE0)
(d) Timer output level register 0 (TOL0)
(e) Timer output mode register 0 (TOM0)
When Multiple PWM Output Function (Slave Channel) Is Used (Output Two Types of PWMs)
TOMq
CKSp
CKSq
TOEq
TOLq
Bit q
Bit q
Bit q
Bit q
TOq
1/0
1/0
1/0
1/0
1/0
15
15
1
n = 00, 02, 04, 06, 08, 10 n < p < q ≤ 11 (However, p and q are consecutive integers.)
Operation clock selection
TOEp
TOLp
TOMp
Bit p
Bit p
Bit p
Bit p
TOp
1/0
1/0
1/0
14
14
0: Selects CK00 (channels 0 to 7) or CK02 (channels 8 to 11) as operation clock of channels p and q.
1: Selects CK01 (channels 0 to 7) or CK03 (channels 8 to 11) as operation clock of channels p and q.
0
0
1
* Make the same setting as master channel.
CCS1p
CCS1q
13
13
0
0
CCS0p
CCS0q
0: Outputs 0 from TOp or TOq.
1: Outputs 1 from TOp or TOq.
0: Stops the TOp or TOq output operation by counting operation.
1: Enables the TOp or TOq output operation by counting operation.
0: Positive logic output (active-high)
1: Inverted output (active-low)
1: Sets slave channel output mode.
12
12
Figure 6-69. Example of Set Contents of Registers
0
0
Count clock selection
TERp
TERq
MAS
MAS
11
11
00B: Selects operation clock.
0
0
CHAPTER 6 TIMER ARRAY UNIT TAUS
Slave/master selection
STSp2
STSq2
10
10
0: Slave channel
1
1
User’s Manual U19678EJ1V1UD
STSp1
STSq1
0
0
9
9
Start trigger selection
STSp0
STSq0
100B: Selects INTTMn of master channel.
8
0
8
0
CISp1
CISq1
7
0
7
0
CISp0
CISq0
6
0
6
0
Selection of TIp and TIq pin input edge
00B: Sets 00B because these are not used.
Operation mode of channel p, q
0100B: One-count mode
5
0
5
0
MDp4
MDq4
4
0
4
0
Start trigger during operation
MDp3
MDq3
1: Trigger input is valid.
3
1
3
1
MDp2
MDq2
2
0
2
0
MDp1
MDq1
1
0
1
0
MDp0
MDq0
0
0
1
1
357

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