UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 722

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.6.4 LIN reception
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
720
Remark
Support of LIN communication
Target channel
Pins used
Interrupt
Error interrupt
Error detection flag
Transfer data length
Transfer rate
Data phase
Parity bit
Stop bit
Data direction
Of UART reception, UART0 supports LIN communication.
For LIN reception, channel 1 of unit (SAU) is used.
Figure 13-87 outlines a reception operation of LIN.
specifications (see CHAPTER 28 ELECTRICAL SPECIFICATIONS).
f
f
MCK
CLK
UART
: System clock frequency
: Operation clock frequency of target channel
Supported
Channel 1 of SAU
RxD0
INTSR0
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
INTSRE0
• Framing error detection flag (FEF01)
• Parity error detection flag (PEF01)
• Overrun error detection flag (OVF01)
8 bits
Max. f
Forward output (default: high level)
Reverse output (default: low level)
The following selectable
• No parity bit (The parity bit is not checked.)
• Appending 0 parity (The parity bit is not checked.)
• Even-parity check
• Odd-parity check
The following selectable
• Appending 1 bit
• Appending 2 bits
MSB or LSB first
MCK
/6 [bps] (SDR01 [15:9] = 2 or more), Min. f
CHAPTER 13 SERIAL ARRAY UNIT
User’s Manual U19678EJ1V1UD
UART0
Not supported
CLK
/(2 × 2
11
× 128) [bps]
UART1
−
−
−
−
Note