UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 236

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

234
Address: FFFA2H
Symbol
OSTC
Figure 5-6. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Remark f
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST8 and
MOST
MOST
8
0
1
1
1
1
1
1
1
1
7
8
After reset: 00H
MOST
MOST
9
0
0
1
1
1
1
1
1
1
6
9
2. The oscillation stabilization time counter counts up to the oscillation
3. The X1 clock oscillation stabilization wait time does not include the time until
X
: X1 clock oscillation frequency
remain 1.
stabilization time set by OSTS.
In the following cases, set the oscillation stabilization time of OSTS to the value
greater than the count value which is to be checked by the OSTC register after
the oscillation starts.
• If the X1 clock starts oscillation while the internal high-speed oscillation clock
• If the STOP mode is entered and then released while the internal high-speed
clock oscillation starts (“a” below).
MOST
MOST
or subsystem clock is being used as the CPU clock.
oscillation clock is being used as the CPU clock with the X1 clock oscillating.
(Note, therefore, that only the status up to the oscillation stabilization time set
by OSTS is set to OSTC after the STOP mode is released.)
10
10
0
0
0
1
1
1
1
1
1
5
X1 pin voltage
waveform
MOST
MOST
CHAPTER 5 CLOCK GENERATOR
R
11
11
0
0
0
0
1
1
1
1
1
4
User’s Manual U19678EJ1V1UD
MOST
MOST
STOP mode release
13
13
0
0
0
0
0
1
1
1
1
3
MOST
MOST
15
15
0
0
0
0
0
0
1
1
1
2
a
MOST
MOST
17
17
0
0
0
0
0
0
0
1
1
1
MOST
MOST
18
18
0
0
0
0
0
0
0
0
1
0
2
2
2
2
2
2
2
2
2
8
8
9
10
11
13
15
17
18
/f
/f
/f
/f
/f
/f
/f
/f
/f
Oscillation stabilization time status
X
X
X
X
X
X
X
X
X
max. 25.6
min.
min.
min. 102.4
min. 204.8
min. 819.2
min. 3.27 ms min. 1.64 ms min.
min. 13.11 ms min. 6.55 ms min.
min. 26.21 ms min. 13.11 ms min.
25.6
51.2
f
X
= 10 MHz
μ
μ
μ
s max. 12.8
s min.
s min.
μ
μ
μ
s min. 51.2
s min. 102.4
s min. 409.6
12.8
25.6
f
X
= 20 MHz
μ
μ
μ
μ
μ
μ
s max.
s min.
s min.
s min.
s min.
s min.