UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 806

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

804
Note The wait time is calculated as follows.
Remark IICWL: IICA low-level width setting register
(IICWL setting value + IICWH setting value + 4) + t
D
IICWH: IICA high-level width setting register
t
f
F
CLK
:
:
IICBSY = 0?
SDA0 and SCL0 signal falling times (see CHAPTER 28 ELECTRICAL SPECIFICATIONS)
CPU/peripheral hardware clock frequency
MSTS = 1?
STCF = 0?
STT = 1
STT = 1
Wait
Wait
C
C
A
B
Note
Figure 14-29. Master Operation in Multi-Master System (2/3)
Yes
Yes
Yes
Enables reserving communication.
Disables reserving communication.
Wait state after stop condition
was detected and start condition
was generated by the communication
reservation function.
No
No
No
CHAPTER 14 SERIAL INTERFACE IICA
Prepares for starting communication
(generates a start condition).
Secure wait time
Prepares for starting communication
(generates a start condition).
User’s Manual U19678EJ1V1UD
Note
by software.
No
F
× 2 × f
EXC = 1 or COI =1?
EXC = 1 or COI =1?
interrupt occurs?
interrupt occurs?
Slave operation
Slave operation
CLK
INTIICA
INTIICA
[clocks]
Yes
Yes
Yes
Yes
No
No
No
Waits for bus release
(communication being reserved).
Waits for bus release
Detects a stop condition.
D