UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 238

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

236
Address: FFFA3H
Symbol
OSTS
Remark f
Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set the
Figure 5-7. Format of Oscillation Stabilization Time Select Register (OSTS)
OSTS2
7
0
0
0
0
0
1
1
1
1
After reset: 07H
2. Setting the oscillation stabilization time to 20
3. Change the setting of the OSTS register before setting the MSTOP bit of the
4. Do not change the value of the OSTS register during the X1 clock oscillation
5. The oscillation stabilization time counter counts up to the oscillation
6. The X1 clock oscillation stabilization wait time does not include the time until
X
: X1 clock oscillation frequency
OSTS register before executing the STOP instruction.
clock operation status control register (CSC) to 0.
stabilization time.
stabilization time set by OSTS.
In the following cases, set the oscillation stabilization time of OSTS to the value
greater than the count value which is to be checked by the OSTC register after
the oscillation starts.
• If the X1 clock starts oscillation while the internal high-speed oscillation clock
• If the STOP mode is entered and then released while the internal high-speed
clock oscillation starts (“a” below).
OSTS1
or subsystem clock is being used as the CPU clock.
oscillation clock is being used as the CPU clock with the X1 clock oscillating.
(Note, therefore, that only the status up to the oscillation stabilization time set
by OSTS is set to OSTC after the STOP mode is released.)
6
0
0
0
1
1
0
0
1
1
X1 pin voltage
waveform
CHAPTER 5 CLOCK GENERATOR
R/W
OSTS0
User’s Manual U19678EJ1V1UD
5
0
0
1
0
1
0
1
0
1
STOP mode release
2
2
2
2
2
2
2
2
8
9
10
11
13
15
17
18
/f
/f
/f
/f
/f
/f
/f
/f
X
X
X
X
X
X
X
X
4
0
a
Oscillation stabilization time selection
3
0
25.6
51.2
102.4
204.8
819.2
3.27 ms
13.11 ms
26.21 ms
f
X
μ
μ
μ
μ
μ
= 10 MHz
s
s
OSTS2
μ
s
s
s
s or less is prohibited.
2
OSTS1
Setting prohibited
25.6
51.2
102.4
409.6
1.64 ms
6.55 ms
13.11 ms
1
f
X
μ
μ
μ
μ
= 20 MHz
s
s
s
s
OSTS0
0