UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 244

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(8) Operation speed mode control register (OSMC)
242
This register is used to control the step-up circuit of the flash memory for high-speed operation.
If the microcontroller operates on a system clock of 10 MHz or more, set this register to 01H.
If the microcontroller operates at low speed on a system clock of 10 MHz or less, power consumption can be
reduced, because the voltage booster can be stopped by setting this register to its initial value, 00H.
OSMC can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Address: F00F3H
Symbol
OSMC
Cautions 1. OSMC can be written only once after reset release, by an 8-bit memory
FSEL
Figure 5-10. Format of Operation Speed Mode Control Register (OSMC)
7
0
0
1
After reset: 00H
2. Write “1” to FSEL before the following two operations.
3. The CPU waits (140.5 clock (f
4. To increase f
5. Set FSEL to 0 when the microcontroller operates on 10 MHz or less.
6. Set FSEL = 0 to shift to STOP mode while V
7. When the FSEL bit of the OSMC register has been set to 1, do not enable (DENn
Operates at a frequency of 10 MHz or less (default).
Operates at a frequency higher than 10 MHz.
manipulation instruction.
• Changing the clock prior to dividing f
• Operating the DMA controller.
Interrupt requests issued during a wait will be suspended.
However, counting the oscillation stabilization time of f
the CPU is waiting.
or more clocks have elapsed.
= 1) DMA operation for at least three clocks after the setting.
speed oscillation clock frequency f
6
0
CHAPTER 5 CLOCK GENERATOR
R/W
CLK
User’s Manual U19678EJ1V1UD
5
0
to 10 MHz or higher, set FSEL to “1”, then change f
4
0
f
CLK
CLK
frequency selection
)). when “1” is written to the FSEL bit.
3
0
IH
.
CLK
DD
to a clock other than Internal high-
= 2.7 V.
2
0
X
can continue even while
1
0
CLK
FSEL
0
after three