UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 399

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

TAUS
default
setting
Channel
default
setting
Operation
start
During
operation
Operation
stop
Remark n = 01 to 10 (78K0R/IB3: n = 01 to 07)
Real-time output trigger generation channel (TRCn = 1)
Sets the TAU0EN and TAUOPEN bits of the PER2
register to 1.
Sets the TPS0 register.
Real-time output channel (TRCm = 0)
Sets the TOEn and TOEm bits to 1 and enables output
of TOn and TOm.
Clears the port register and port mode register to 0.
Sets the TOEn and TOEm bits to 1 (only when operation
is resumed).
Sets the TSn bit of the trigger generation channel to 1.
The TMRn register can only change the set values of
the CISn1 and CISn0 bits.
Set values of the TROn and TROm bits can be
changed.
The TTn bit is set to 1.
The TOEn and TOEm bits are cleared to 0 and values
are set to the TOn and TOm bits.
Determines the clock frequencies of CK00 and CK01
for channels 0 to 7, and those of CK02 and CK03 for
channels 8 to 11.
Sets the TMRn register (determines operation mode
of channel).
Sets the TRCm bit to 1 (trigger generation channel).
Sets the TREm bit to 1 (real-time output enable).
Sets the TRCm bit to 0 (non-trigger generation
channel).
Sets the TREm bit to 1 (real-time output enable).
The TSn bit automatically returns to 0 because it is a
trigger bit.
The TTn bit automatically returns to 0 because it is a
trigger bit.
m = 02 to 11 (78K0R/IB3: m = 02 to 07)
Figure 7-22. Operation Procedure of Real-Time Output Function (Type 2) (1/2)
Software Operation
CHAPTER 7 INVERTER CONTROL FUNCTIONS
User’s Manual U19678EJ1V1UD
Power-off status
Power-on status. Each channel stops operating.
Channel stops operating.
(Clock is supplied and some power is consumed.)
The TOn and TOm pins go into Hi-Z output state.
TOn and TOm do not change because channel has stopped
operating.
The TOn and TOm pins of the product output the TOn and
TOm set levels.
Real-time output trigger generation channel (TRCn = 1)
TEn = 1, and count operation starts.
Counter (TCRn) counts up from 0000H and transfers
(captures) the count value to TDRn when the valid edge of
the TIn pin input is detected. At the same time, TCRn is
cleared to 0000H and INTTMn is generated.
The OVF bit of the TSRn register is set or cleared when an
overflow occurs or does not occur at this time. After that, the
above operation is repeated.
The set value of TROm of the real-time output channel is
output from TOm at the INTTMn output timing.
TEn = 0, and count operation stops.
The TOn and TOm pins output the set levels of TOn and
TOm.
(Clock supply is stopped and writing to each register is
disabled.)
(Clock supply is started and writing to each register is
enabled.)
Clears TCRn to 0000H by count clock input. INTTMn is
generated if the MDn0 bit of the TMRn register is 1.
TCRn holds count value and stops.
TCRn also holds the OVF bit of the TSRn register.
The TOn output is not initialized but holds current status
and stops.
Hardware Status
397