UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 322

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

320
Figure 6-38. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (2/3)
TMRn
TPS0
(2) When f
TIS0
TO0
(a) Timer mode register n (TMRn)
(b) Timer clock select register 0 (TPS0)
(c) Timer input select register 0 (TIS0)
(d) Timer output register 0 (TO0)
Remarks 1. n = 00 to 11, k = 0 to 3
Bits 7 to 4, 3 to 0
PRS0k3 to PRS0k0
CKSn
Bit n
Bit n
TISn
TOn
1/0
1/0
15
1
SUB
0000
Operation clock selection
2. f
/4 is selected as count clock (products other than 78K0R/IB3)
14
0: Selects CK00 (channels 0 to 7) or CK02 (channels 8 to 11) as operation clock of channel n.
1: Selects CK01 (channels 0 to 7) or CK03 (channels 8 to 11) as operation clock of channel n.
0
f
CLK
SUB
CCS1n
1: Selects subsystem clock divided by four (f
0: Outputs 0 from TOn.
1: Outputs 1 from TOn.
(no division) is selected as selected operation clock by TPS0 register.
13
: Subsystem clock oscillation frequency
0
0000B: Selects f
k = 0 (bits 0 to 3) if CK00 is selected, k = 1 (bits 4 to 7) if CK01 is selected, k = 2 (bits 8 to 11) if CK02
is selected, and k = 3 (bits 12 to 15) if CK03 is selected.
CCS0n
12
1
Count clock selection
TERn
MAS
11
01B: Selects subsystem clock divided by four (f
0
CHAPTER 6 TIMER ARRAY UNIT TAUS
CLK
Slave/master selection
STSn2
10
0: Independent channel operation function
(no division) as operation clock selected by CKSn of TMRn register.
0
User’s Manual U19678EJ1V1UD
STSn1
9
0
Start trigger selection
STSn0
000B: Selects only software start.
8
0
CISn1
1/0
SUB
7
/4).
CISn0
1/0
6
f
SUB
00B: Detects falling edge (counts on f
01B: Detects rising edge (counts on f
10B: Detects both edges (counts on f
11B: Setting prohibited
Operation mode of channel n
/4 edge selection
0000B: Interval timer
0
5
Setting of operation when counting is started
0: Neither generates INTTMn nor inverts
1: Generates INTTMn and inverts timer
SUB
MDn4
timer output when counting is started.
output when counting is started.
/4).
4
0
MDn3
3
0
MDn2
2
0
MDn1
1
0
SUB
SUB/
SUB
MDn0
1/0
0
/4 cycles).
/4 cycles).
2 cycles).