UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 756

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note 1
SE
00
0
1
Notes 1. The serial channel enable register 0 (SE0) is a read-only status register which is set using the serial
754
Remark X: Don’t care
MD
002
(3) 44-pin and 48-pin products of 78K0R/IC3, 78K0R/ID3, 78K0R/IE3
0
0
0
0
Table 13-7. Relationship Between Register Settings and Pins (Channel 0: CSI00, UART0 Transmission)
4. This is 0 or 1, depending on the communication operation. For details, refer to 13.3 (12) Serial output
2. When channel 1 is set to UART0 reception, this pin becomes an RxD0 function pin (refer to Table 13-10). In
3. This pin can be set as a port function pin.
5. When using UART0 transmission and reception in a pair, set channel 1 to UART0 reception (refer to Table
MD0
01
0
1
0
1
channel start register 0 (SS0) and serial channel stop register 0 (ST0).
this case, operation stop mode or UART0 transmission must be selected for channel 0.
register 0 (SO0).
13-10).
SOE
00
0
0
1
1
0
1
1
1
SO0
Note 4
Note 4
Note 4
Note 4
Note 4
0/1
0/1
0/1
0/1
0/1
0
1
1
1
CKO
Note 4
Note 4
Note 4
0/1
0/1
0/1
00
1
1
1
1
1
TXE
00
0
0
1
1
0
1
1
1
RXE
00
0
1
0
1
1
0
1
0
Note 3
Note 3
PM
75
CHAPTER 13 SERIAL ARRAY UNIT
×
×
1
1
1
0
0
0
Note 3
Note 3
P75 PM
×
×
×
×
1
1
1
×
User’s Manual U19678EJ1V1UD
Note 2
Note 3
Note 3
Note 3
Note 3
74
×
1
×
1
1
×
1
×
Note 2
Note 3
Note 3
Note 3
Note 3
P74
×
×
×
×
×
×
×
×
Note 3
Note 3
Note 3
PM
73
×
×
0
0
×
0
0
0
Note 3
Note 3
Note 3
P73 Operation mode
×
×
1
1
×
1
1
1
Operation stop
Master CSI00
Master CSI00
Master CSI00
transmission
Slave CSI00
Slave CSI00
Slave CSI00
transmission
transmission
/reception
transmission
transmission
/reception
reception
reception
UART0
mode
Note 5
TI11/P75
TI11/P75
TI11P75
(output)
(output)
(output)
SCK00/
SCK00
SCK00
SCK00
SCK00
SCK00
SCK00
(input)
(input)
(input)
RxD0/TI10 /
RxD0/TI10 /
RxD0/TI10/
Pin Function
TI10/P74
TI10/P74
TI10/P74
P74
SI00/
SI00
SI00
SI00
SI00
P74
P74
Note 2
TxD0/TO10/
TO10/P73
TO10/P73
TI10/P73
SO00/
SO00
SO00
SO00
SO00
TxD0
P73