UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 661

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.5.3 Master transmission/reception
other device.
Notes
Remark n: Channel number (n = 2 (78K0R/IB3 and 38-pin products of 78K0R/IC3), n = 0 to 2 (44-pin and 48-pin
Target channel
Pins used
Interrupt
Error detection flag
Transfer data length
Transfer rate
Data phase
Clock phase
Data direction
Master transmission/reception is that the 78K0R/Ix3 outputs a transfer clock and transmits/receives data to/from
3-Wire Serial I/O
1. CSI00 and CSI01 are only available in the 44-pin and 48-pin products of the 78K0R/IC3 and in the
2. Use this operation within a range that satisfies the conditions above and the AC characteristics in the
products of 78K0R/IC3, 78K0R/ID3, and 78K0R/IE3))
78K0R/ID3 and 78K0R/IE3.
electrical specifications (see CHAPTER 28 ELECTRICAL SPECIFICATIONS).
Channel 0 of SAU
SCK00, SI00, SO00
INTCSI00
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
Overrun error detection flag (OVF0n) only
7 or 8 bits
Max. f
Selectable by DAP0n bit of SCR0n register
• DAP0n = 0: Data I/O starts at the start of the operation of the serial clock.
• DAP0n = 1: Data I/O starts half a clock before the start of the serial clock operation.
Selectable by CKP0n bit of SCR0n register
• CKP0n = 0: Forward
• CKP0n = 1: Reverse
MSB or LSB first
CLK
/4 [Hz], Min. f
CSI00
Note
CHAPTER 13 SERIAL ARRAY UNIT
CLK
User’s Manual U19678EJ1V1UD
/(2 × 2
11
× 128) [Hz]
Channel 1 of SAU
SCK01, SI01, SO01
INTCSI01
Note
CSI01
f
CLK
Note
: System clock frequency
Channel 2 of SAU
SCK10, SI10, SO10
INTCSI10
CSI10
659