UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 805

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Master operation in multi-master system
Note Confirm that the bus is released (CLD bit = 1, DAD bit = 1) for a specific period (for example, for a period of
1
No
one frame). If the SDA0 pin is constantly at low level, decide whether to release the I
SDA0 pins = high level) in conformance with the specifications of the product that is communicating.
Setting STCEN and IICRSV
ACKE = WTIM = SPIE = 1
IICCTL0 ← 0XX111XXB
IICCTL0 ← 1XX111XXB
Checking bus status
IICWL, IICWH ← XXH
Enables reserving
interrupt occurs?
Master operation
communication.
SVA ← XXH
IICRSV = 0?
IICF ← 0XH
Setting port
Setting port
SPD = 1?
SPIE = 1
IICE = 1
INTIICA
START
starts?
A
Yes
Yes
Yes
Yes
(Communication start request)
•
•
Bus status is
being checked.
Waiting to be specified as a slave by other master
Waiting for a communication start request (depends on user program)
Figure 14-29. Master Operation in Multi-Master System (1/3)
Note
Disables reserving
communication.
(No communication start request)
No
No
No
Selects a transfer clock.
Sets a local address.
Sets a start condition.
Releases the bus for a specific period.
Setting of the port used alternatively as the pin to be used.
First, set the port to input mode and the output latch to 0 (see 14.3 (8) Port mode register 6 (PM6)).
Slave operation
Set the port from input mode to output mode and enable the output of the I
(see 14.3 (8) Port mode register 6 (PM6)).
B
CHAPTER 14 SERIAL INTERFACE IICA
User’s Manual U19678EJ1V1UD
STCEN = 1?
Yes
interrupt occurs?
Slave operation
SPIE = 0
INTIICA
Yes
No
Waits for a communication request.
No
interrupt occurs?
SPD = 1?
SPT = 1
INTIICA
Yes
Yes
2
C bus
No
No
Waits for detection
of the stop condition.
Prepares for starting
communication
(generates a stop condition).
Slave operation
2
C bus (SCL0 and
803