UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 660

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

658
Caution
Remark
Writing 1 to MD0n0 bit
Figure 13-39. Flowchart of Master Reception (in Continuous Reception Mode)
<1> to <8> in the figure correspond to <1> to <8> in Figure 13-38 Timing Chart of Master
Reception (in Continuous Reception Mode).
After setting SAU0EN bit of the peripheral enable register 0 (PER0) to 1, be sure to set
serial clock select register 0 (SPS0) after 4 or more f
<3>
<6>
Yes
No
SMR0n, SCR0n:
SDR0n[15:9]:
SO0
<2>
<4>
<5>
<7>
<8>
CHAPTER 13 SERIAL ARRAY UNIT
Writing dummy data to SIOp
Reading receive data from
Reading receive data from
Clearing SAU0EN bit of PER0
User’s Manual U19678EJ1V1UD
Setting SAU0EN bit of PER0
Starting CSI communication
Clearing 0 to MD0n0 bit
Setting transfer rate by
Communication continued?
End of communication
Writing 1 to SS0n bit
SIOp (=SDR0n[7:0])
SIOp (=SDR0n[7:0])
Writing 1 to ST0n bit
Port manipulation
The following is the last
Buffer empty interrupt
Transfer end interrupt
(=SDR0n[7:0])
SPS0 register
Setting communication
Setting transfer rate
Setting output and SCKp output
No
TSF0n = 1?
Yes
Yes
register to 1
register to 0
receive data?
generated?
generated?
Yes
No
No
No
Yes
CLK
Perform initial setting when SE0n = 0.
<1> Select the buffer empty interrupt.
clocks have elapsed.