UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 312

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.5.2 TOn pin output setting
operation start.
6.5.3 Cautions on channel output operation
the values set in TO0, TOE0, TOL0, and TOM0 does not affect the timer operation, the values can be changed during
timer operation. To output an expected waveform from the TOn pin by timer operation, however, set TO0, TOE0, TOL0,
and TOM0 to the values stated in the register setting example of each operation.
occurrence of the timer interrupt (INTTMn) of each channel, the waveform output to the TOn pin might differ,
depending on whether the values are changed immediately before or immediately after the timer interrupt (INTTMn)
occurs.
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The following figure shows the procedure and status transition of TOn out put pin from initial setting to timer
(1) Changing values set in registers TO0, TOE0, TOL0, and TOM0 during timer operation
Since the timer operations (operations of TCRn and TDRn) are independent of the TOn output circuit and changing
When the values set to the TOE0, TOL0, and TOM0 registers (but not the TO0 register) are changed close to the
Remark
Remark
<1> The operation mode of timer output is set.
<2> The timer output signal is set to the initial status by setting TO0 register.
<3> The timer output operation is enabled by writing 1 to TOEn (writing to TO0 register is disabled).
<4> The port I/O setting is set to output (see 6.3 (26) Port mode registers 0, 1, 3, 5, 7).
<5> The timer operation is enabled (TSn = 1).
• TOMn bit (0: Master channel output mode, 1: Slave channel output mode)
• TOLn bit (0: Forward output, 1: Reverse output)
Timer alternate-function pin
n = 00 to 11 (n = 02 to 07 and 11 for timer output pin (TOn) of 78K0R/IB3)
n = 00 to 11 (n = 02 to 07 and 11for the timer output pin (TOn) of 78K0R/IB3)
Figure 6-26. Status Transition from Timer Output Setting to Operation Start
Timer output signal
(Counter)
TCRn
TOEn
TOn
CHAPTER 6 TIMER ARRAY UNIT TAUS
<1> Set the TOMn
Write operation enabled period to TOn
Set the TOLn
User’s Manual U19678EJ1V1UD
Undefined value (FFFFH after reset)
<2> Set the TOn
Hi-Z
<3> Set the TOEn
Write operation disabled period to TOn
<4> Set the port to
output mode
<5> Timer operation start