UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 259

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(4) CPU operating with 40 MHz internal high-speed oscillation clock (J) after reset release (A)
(5) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C)
Status Transition
(A) → (B) → (J)
Status Transition
(B) → (C)
(X1 clock: 2 MHz ≤ fX ≤ 10 MHz)
(B) → (C)
(B) → (C)
(external main clock)
(X1 clock: 10 MHz < fX ≤ 20 MHz)
Notes 1. The CMC register can be changed only once after reset release. This setting is not necessary if it
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set
Remark (A) to (K) in Table 5-5 correspond to (A) to (K) in Figure 5-15 and Figure 5-16.
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
2. Set the oscillation stabilization time as follows.
3. FSEL = 1 when f
(Setting sequence of SFR registers)
(see CHAPTER 28 ELECTRICAL SPECIFICATIONS).
has already been set.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by OSTS
If a divided clock is selected and f
Table 5-5. CPU Clock Transition and SFR Register Setting Examples (2/6)
Setting Flag of SFR Register
CLK
> 10 MHz
EXCLK
CHAPTER 5 CLOCK GENERATOR
Unnecessary if these registers
0
0
1
CMC Register
User’s Manual U19678EJ1V1UD
are already set
CLK
OSCSEL
DSCCTL
Register
DSCON
1
1
1
≤ 10 MHz, use with FSEL = 0 is possible even if f
1
Note 1
AMPH
0/1
0
1
Stabilization
Waiting for
Necessary
Oscillation
(100
Register
Note 2
Note 2
Note 2
OSTS
Unnecessary if the CPU is operating with
μ
s)
the high-speed system clock
MSTOP
Register
CSC
0
0
0
DSCCTL
Register
DSPO
OSMC
Register
FSEL
1
1
0/1
Note 3
0
Register
checked
checked
checked
Must be
Must be
OSTC
not be
Must
X
> 10 MHz.
DSCCTL
SELDSC
Register
MCM0
1
CKC
Regi
ster
1
1
1
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