UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 332

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remark
330
TAUS
default
setting
Channel
default
setting
Operation
start
During
operation
Operation
stop
TAUS
stop
n = 00, 10, 11 (44-pin and 48-pin products of 78K0R/IC3: n = 10 and 11)
Sets the TAU0EN bit of the PER2 register to 1.
Sets the TPS0 register.
Sets the TMRn register (determines the operation mode
of the channel and selects the detection edge).
Sets interval (period) value to the TDRn register.
Clears the TOMn bit of the TOM0 register to 0 (master
channel output mode).
Clears the TOLn bit to 0.
Sets the TOn bit and determines default level of the TOn
output.
Sets TOEn to 1 and enables operation of TOn.
Clears the port register and port mode register to 0.
Sets the TOEn to 1 (only when operation is resumed).
Sets the TSn bit to 1.
Set value of the TDRn register can be changed.
The TCRn register can always be read.
The TSRn register is not used.
Set values of TO0 and TOE0 registers can be changed.
Set values of TMRn register, TOMn, and TOLn bits
cannot be changed.
The TTn bit is set to 1.
TOEn is cleared to 0 and value is set to the TO0n bit.
To hold the TOn pin output level
When holding the TOn pin output level is not
necessary
The TAU0EN bit of the PER2 register is cleared to 0.
Determines the clock frequencies of CK00 and CK01
for channels 0 to 7, and those of CK02 and CK03 for
channels 8 to 11.
The TSn bit automatically returns to 0 because it is a
trigger bit.
The TTn bit automatically returns to 0 because it is a
trigger bit.
Clears TOn bit to 0 after the value to
be held is set to the port register.
Switches the port mode register to input mode.
Figure 6-47. Operation Procedure When Frequency Divider Function Is Used
Software Operation
CHAPTER 6 TIMER ARRAY UNIT TAUS
User’s Manual U19678EJ1V1UD
Power-off status
Power-on status. Each channel stops operating.
Channel stops operating.
(Clock is supplied and some power is consumed.)
The TOn pin goes into Hi-Z output state.
The TOn default setting level is output when the port mode
register is in output mode and the port register is 0.
TOn does not change because channel stops operating.
The TOn pin outputs the TOn set level.
TEn = 1, and count operation starts.
Counter (TCRn) counts down. When count value reaches
0000H, the value of TDRn is loaded to TCRn again, and the
count operation is continued. By detecting TCRn = 0000H,
INTTMn is generated and TOn performs toggle operation.
After that, the above operation is repeated.
TEn = 0, and count operation stops.
The TOn pin outputs the TOn set level.
The TOn pin output level is held by port function.
The TOn pin output level goes into Hi-Z output state.
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
(Clock supply is started and writing to each register is
enabled.)
Value of TDRn is loaded to TCRn at the count clock input.
INTTMn is generated and TOn performs toggle operation if
the MDn0 bit of the TMRn register is 1.
TCRn holds count value and stops.
The TOn output is not initialized but holds current status.
All circuits are initialized and SFR of each channel is also
initialized.
(The TOn bit is cleared to 0 and the TOn pin is set to port
mode).
Hardware Status