UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 227

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

X2/EXCLK
XT2//P124
Note
XT1/P123
Clock operation mode
X1/P121
/P122
control register
48-pin products of 78K0R/IC3, 78K0R/ID3 and 78K0R/IE3 only.
(CMC)
AMPH
Crystal/ceramic
(40 MHz (TYP.))
External input
(8 MHz (typ.))
OSCSELS
High-speed system
high-speed oscillator
high-speed
Internal high-speed
high-speed
oscillation
oscillation
oscillation
oscillation
Internal
Internal
Subsystem clock
EXCLK OSCSEL
40 MHz internal
Crystal
clock oscillator
clock
oscillator
oscillator
Clock operation mode
control register
(CMC)
f
f
IH40
f
f
f
EX
IH8
XT
X
Clock operation status
f
f
MX
f
f
IH
DSC
SUB
control register
Clock operation status
(CSC)
(30 kHz (typ.))
Internal low-speed
low-speed
oscillation
CLS
control register
Internal
oscillator
MSTOP
(CSC)
Figure 5-1. Block Diagram of Clock Generator (78K0R/IC3, 78K0R/ID3, 78K0R/IE3)
XTSTOP HIOSTOP
STOP mode
signal
f
IL
DSCS
MOST
SELDSC
8
Option byte
WDTON
WDSTBYON
MOST
HALT/STOP mode signal
9
stabilization time counter
OSTS2
MOST
10
X1 oscillation
DSPO
(
000C0H
MOST
40 MHz internal high-speed
oscillation control register
(DSCCTL)
11
OSTS1 OSTS0
MOST
3
13
)
DSCON
Oscillation stabilization time
counter status register
(OSTC)
Oscillation stabilization
time select register (OSTS)
MOST
15
MOST
17
MOST
18
Main system
clock source
selection
Internal bus
Internal bus
f
MAIN
CLS
OACMP
Clock output/
buzzer output
EN
CSS
Peripheral enable register 1
(PER1)
f
f
f
f
f
f
f
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
SUB
/2
/2
/2
/2
/2
/2
MCS
5
4
3
2
MCM0
Watchdog timer
Real-time counter,
clock output/buzzer output
SAU0
EN
System clock control
register (CKC)
1
MD
IV2
CPU clock and
hardware clock
IICA
EN
Selection of
peripheral
4
source
MD
IV1
ADC
EN
Peripheral enable register 0
(PER0)
MD
IV0
f
CLK
RTC
EN
(see CHAPTER 18)
Standby controller
operation mode
STOP mode
HALT mode
Nomarl
f
f
CLK
CLK
/2
Controller
TAU0
EN
Timer array unit TAUS
Timer array unit option
CPU
TAUOP
Serial array unit
Serial interface IICA
Real-time counter
A/D converter
Programmable gain amplifier/
comparator
EN
Peripheral enable register 2
(PER2)
Note