UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 255

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.6.4 Example of setting XT1 oscillator (products other than 78K0R/IB3)
oscillation clock. To subsequently change the clock to the XT1 oscillation clock, set the oscillator and start oscillation
by using the operation speed mode control register (OSMC), clock operation mode control register (CMC), and clock
operation status control register (CSC), set the XT1 oscillation clock to f
(CKC).
<5> Use the OSTC register to wait for oscillation of the X1 oscillator to stabilize.
<6> Use the MCM0 bit of the CKC register to specify the X1 oscillation clock as the CPU/peripheral hardware clock.
<7> Wait until the MCS bit changes to 1.
After a reset release, the CPU/peripheral hardware clock (f
[Register settings] Set the register in the order of <1> to <6> below.
<1> Use the OSMC register to set the frequency of the CPU/peripheral hardware.
<2> Set (1) the OSCSELS bit of the CMC register to operate the XT1 oscillator.
<3> Clear (0) the XTSTOP bit of the CSC register to start oscillating the XT1 oscillator.
<4> Use the timer function or another function to wait for oscillation of the subsystem clock to stabilize by using
<5> Use the CSS bit of the CKC register to specify the XT1 oscillation clock as the CPU/peripheral hardware clock.
<6> Wait until the CLS bit changes to 1.
Example: Wait until the bits reach the following values when a wait of at least 102.4
Use the MDIV2 to MDIV0 bits to specify the division ratio.
OSMC
software.
OSTC
CMC
CKC
CSC
CKC
Note
10 MHz resonator.
MSTOP
MOST8
CLS
EXCLK
CLS
7
1
7
0
7
0
7
0
7
1
7
0
Note
CLS bit is not provided in the 78K0R/IB3. In the 78K0R/IB3, bit 7 is fixed to 0.
OSCSEL
XTSTOP
MOST9
CSS
CSS
6
1
6
0
6
0
6
0
6
0
6
1
CHAPTER 5 CLOCK GENERATOR
MOST10
MCS
MCS
User’s Manual U19678EJ1V1UD
1
0
0
0
0
0
5
5
5
5
5
5
OSCSELS
MOST11
MCM0
MCM0
4
0
4
1
4
0
4
1
4
0
4
0
CLK
) always starts operating with the internal high-speed
MOST13
3
0
3
1
3
0
3
0
3
0
3
1
CLK
by using the system clock control register
MOST15
MDIV2
MDIV2
0/1
2
0
2
2
0
2
0
2
0
2
0
μ
MOST17
MDIV1
MDIV1
s is set based on a
0/1
1
0
1
1
0
1
0
1
0
1
0
HIOSTOP
MOST18
MDIV0
MDIV0
AMPH
FSEL
0/1
0
0
0
0
0
0
0
0
0
0
0
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