UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 770

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

768
Address: F0230H
IICCTL0
Symbol
Notes 1. The IICA status register, the STCF and IICBSY bits of the IICF register, and the CLD and DAD
Caution If the operation of I
WREL
Be sure to set this bit (1) while the SCL0 and SDA0 lines are at high level.
Condition for clearing (IICE = 0)
• Cleared by instruction
• Reset
LREL
The standby mode following exit from communications remains in effect until the following communications entry
conditions are met.
• After a stop condition is detected, restart is in master mode.
• An address match or extension code reception occurs after the start condition.
Condition for clearing (LREL = 0)
• Automatically cleared after execution
• Reset
When WREL is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status (TRC =
1), the SDA0 line goes into the high impedance state (TRC = 0).
Condition for clearing (WREL = 0)
• Automatically cleared after execution
• Reset
IICE
IICE
<7>
0
1
0
1
0
1
Notes 2, 3
Notes 2, 3
2. The signal of this bit is invalid while IICE0 is 0.
3. When the LREL and WREL bits are read, 0 is always read.
After reset: 00H
bits of the IICCTL1 register are reset.
is low level, and the digital filter is turned on (DFC of the IICCTL1 register = 1), a start
condition will be inadvertently detected immediately. In this case, set (1) the LREL bit by
using a 1-bit memory manipulation instruction immediately after enabling operation of
I
2
Stop operation. Reset the IICA status register (IICS)
Enable operation.
Normal operation
This exits from the current communications and sets standby mode. This setting is automatically cleared
to 0 after being executed.
Its uses include cases in which a locally irrelevant extension code has been received.
The SCL0 and SDA0 lines are set to high impedance.
The following flags of IICA control register 0 (IICCTL0) and IICA status register (IICS) are cleared to 0.
• STT • SPT • MSTS • EXC • COI • TRC • ACKD • STD
Do not cancel wait
Cancel wait. This setting is automatically cleared after wait is canceled.
C (IICE = 1).
Figure 14-6. Format of IICA Control Register 0 (IICCTL0) (1/4)
LREL
<6>
WREL
<5>
R/W
CHAPTER 14 SERIAL INTERFACE IICA
2
C is enabled (IICE = 1) when the SCL0 line is high level, the SDA0 line
User’s Manual U19678EJ1V1UD
SPIE
<4>
Exit from communications
WTIM
<3>
I
2
C operation enable
Wait cancellation
Condition for setting (IICE = 1)
• Set by instruction
Condition for setting (LREL = 1)
• Set by instruction
Condition for setting (WREL = 1)
• Set by instruction
ACKE
Note 1
<2>
. Stop internal operation.
STT
<1>
SPT
<0>