UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 232

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) System clock control register (CKC)
230
This register is used to select a CPU/peripheral hardware clock and a division ratio.
CKC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 09H.
Address: FFFA4H
Symbol
CKC
Notes 1. Bits 7 and 5 are read-only.
Remarks 1. f
(Cautions 1 to 3 are given on the next page.)
CLS
CLS
MCM0
MCS
CSS
1
<7>
Note 4
0
1
0
1
0
1
0
Note 2
Note 2
2. CLS bit is provided in the 78K0R/IB3. In the 78K0R/IB3, bit 7 is fixed to 0.
3. Setting is prohibited if the high-speed system clock (f
4. Changing the value of the MCM0 bit is prohibited while CSS is set to 1.
After reset: 09H
2. ×:
Figure 5-4. Format of System Clock Control Register (CKC)
clock (f
Main system clock (f
Subsystem clock divided by 2 (f
Internal high-speed oscillation clock (f
(f
High-speed system clock (f
Selects the internal high-speed oscillation clock (f
oscillation clock (f
Selects the internal high-speed oscillation clock (f
f
f
f
IH
IH40
MX
SUB
IH40
:
: High-speed system clock frequency
CSS
<6>
: 40 MHz internal high-speed oscillation clock
: Subsystem clock frequency
)
MDIV2
MAIN
don’t care
Internal high-speed oscillation clock frequency
0
0
0
0
1
1
×
) and if f
Other than above
CHAPTER 5 CLOCK GENERATOR
R/W
MCS
<5>
IH40
User’s Manual U19678EJ1V1UD
MX
Note 1
MAIN
) as the main system clock (f
< 4 MHz.
MDIV1
Status of CPU/peripheral hardware clock (f
)
Main system clock (f
0
0
1
1
0
0
×
MX
Status of Main system clock (f
)
MCM0
<4>
SUB
/2)
IH
) or 40 MHz internal high-speed oscillation clock
MDIV0
0
1
0
1
0
1
×
3
1
MAIN
) operation control
IH
MAIN
MX
) or 40 MHz internal high-speed
) as the main system clock (f
)
f
f
f
f
f
f
f
Setting prohibited
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
SUB
MDIV2
/2
/2 (This is the default setting if
/2
/2
/2
/2
MX
2
MAIN
Selection of CPU/peripheral
2
3
4
5 Note 3
) is selected as the main system
MCM0 = 0.)
)
hardware clock (f
CLK
)
MDIV1
1
MAIN
CLK
)
MDIV0
)
0