UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 852

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.3 Registers to Controlling DMA Controller
850
Address: FFFBAH (DMC0), FFFBBH (DMC1)
DMA controller is controlled by the following registers.
• DMA mode control register n (DMCn)
• DMA operation control register n (DRCn)
Symbol
DMCn
Remark
(1) DMA mode control register n (DMCn)
DMCn is a register that is used to set a transfer mode of DMA channel n. It is used to select a transfer
direction, data size, setting of pending, and start source. Bit 7 (STGn) is a software trigger that starts DMA.
Rewriting bits 6, 5, and 3 to 0 of DMCn is prohibited during operation (when DSTn = 1).
DMCn can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Note The software trigger (STGn) can be used regardless of the IFCn0 to IFCn3 values.
Remark
DMA transfer is performed once by writing 1 to STGn when DMA operation is enabled (DENn = 1).
When this bit is read, 0 is always read.
DMA transfer that has been held pending can be started by clearing the value of DWAITn to 0.
It takes 2 clocks to actually hold DMA transfer pending when the value of DWAITn is set to 1.
n: DMA channel number (n = 0, 1)
STGn
DWAITn
DRSn
STGn
DSn
<7>
0
1
0
1
0
1
0
1
n: DMA channel number (n = 0, 1)
Note
Figure 16-4. Format of DMA Mode Control Register n (DMCn) (1/2)
No trigger operation
DMA transfer is started when DMA operation is enabled (DENn = 1).
SFR to internal RAM
Internal RAM to SFR
8 bits
16 bits
Executes DMA transfer upon DMA start request (not held pending).
Holds DMA start request pending if any.
DRSn
<6>
CHAPTER 16 DMA CONTROLLER
After reset: 00H
DSn
<5>
User’s Manual U19678EJ1V1UD
Specification of transfer data size for DMA transfer
DWAITn
Selection of DMA transfer direction
DMA transfer start software trigger
<4>
R/W
Pending of DMA transfer
IFCn3
3
IFCn2
2
IFCn1
1
IFCn0
0