UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 568

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.4.2 Setting overflow time of watchdog timer
starts counting again by writing “ACH” to WDTE during the window open period before the overflow time.
566
Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows
Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H).
If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer
The following overflow time is set.
Caution The watchdog timer continues its operation during self-programming of the flash memory and
Remark f
EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set the
overflow time and window size taking this delay into consideration.
5. The watchdog timer continues its operation during self-programming of the flash memory
IL
WDCS2
: Internal low-speed oscillation clock frequency
When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts
Therefore, if the period between the STOP mode release and the watchdog timer overflow is
Consequently, set the overflow time in consideration of the oscillation stabilization time
depending on the set value of bit 0 (WDSTBYON) of the option byte (000C0H).
If WDSTBYON = 0, the watchdog timer resumes counting after the HALT or STOP mode is
released. At this time, the counter is cleared to 0 and counting starts.
operating after the oscillation stabilization time has elapsed.
short, an overflow occurs during the oscillation stabilization time, causing a reset.
when operating with the X1 oscillation clock and when the watchdog timer is to be cleared
after the STOP mode release by an interval interrupt.
and EEPROM
Set the overflow time and window size taking this delay into consideration.
In HALT mode
In STOP mode
0
0
0
0
1
1
1
1
Table 10-3. Setting of Overflow Time of Watchdog Timer
WDCS1
0
0
1
1
0
0
1
1
TM
emulation. During processing, the interrupt acknowledge time is delayed.
Watchdog timer operation stops.
CHAPTER 10 WATCHDOG TIMER
WDCS0
0
1
0
1
0
1
0
1
User’s Manual U19678EJ1V1UD
WDSTBYON = 0
2
2
2
2
2
2
2
2
7
8
9
10
12
14
15
17
/f
/f
/f
/f
/f
/f
/f
/f
IL
IL
IL
IL
IL
IL
IL
IL
(3.88 ms)
(7.76 ms)
(15.52 ms)
(31.03 ms)
(124.12 ms)
(496.48 ms)
(992.97 ms)
(3971.88 ms)
Overflow Time of Watchdog Timer
(f
IL
= 33 kHz (MAX.))
Watchdog timer operation continues.
WDSTBYON = 1