UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 382

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

380
(22) TAU option Hi-Z stop trigger register (OPHT)
Address: F0226H
Symbol
OPHT
OPHT sets the Hi-Z controller software trigger. Set this register to 1 to cancel the Hi-Z status of the TO02 to
TO07 pins when the software trigger is set as valid. Because OPHTn is a trigger bit, OPHTn will be cleared as
soon as the Hi-Z cancellation request signal is output.
OPHT can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Caution Be sure to clear bits 15 to 2 to 0.
Remarks 1. When the OPHT register is read, 0000H is always read.
OPH
OPH
T0
15
T1
0
1
0
0
1
Figure 7-13. Format of TAU Option Hi-Z Stop Trigger Register (OPHT)
These bits are invalid other than when OPM = 1 and HSM = 1.
OPM HDM HSM HZIF
OPM HSM HZIF
These bits are invalid other than when OPM = 0 and HDM = 0 or when OPM = 1 and HSM = 1
14
−
0
0
1
1
0
−
1
After reset: 0000H
2. OPM
3. n = 0, 1
HSM
HDM
HZIF0 and 1 : Bits 0 and 1 of TAU option mode register (OPMR)
13
0
−
1
−
0
0
−
−
CHAPTER 7 INVERTER CONTROL FUNCTIONS
12
1
1
0
1
−
0
1
−
−
−
The Hi-Z state of TO06 and TO07 is canceled in synchronization with the PWM
cycle.
The Hi-Z state of TO06 and TO07 cannot be cancelled.
11
0
1
−
0
1
−
−
: Bit 15 of TAU option mode register (OPMR)
: Bit 13 of TAU option mode register (OPMR)
: Bit 12 of TAU option mode register (OPMR)
W
User’s Manual U19678EJ1V1UD
HZIF
0
1
10
0
0
−
−
−
The Hi-Z state of TO02 to TO07 is canceled in synchronization with
the PWM cycle.
The Hi-Z state of TO02 to TO07 cannot be cancelled.
The Hi-Z state of TO02 and TO03 is canceled in synchronization
with the PWM cycle.
The Hi-Z state of TO02 and TO03 cannot be cancelled.
9
0
8
0
Hi-Z control output signal 1
7
0
Hi-Z control output signal 0
6
0
−
5
0
−
4
0
3
0
2
0
OPH
T1
1
OPH
T0
0