UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 262

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(11) CPU clock changing from subsystem clock (D) to high-speed system clock (C) (products other than
(12) CPU clock changing from 40 MHz internal high-speed oscillation clock (J) to internal high-speed
260
(J) → (B)
Status Transition
(D) → (C) (X1 clock: 2 MHz ≤ f
≤ 10 MHz)
(D) → (C) (X1 clock: 10 MHz < f
≤ 20 MHz)
(D) → (C) (external main clock)
Status Transition
(Setting sequence of SFR registers)
78K0R/IB3)
Notes 1.
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set
Remark (A) to (K) in Table 5-5 correspond to (A) to (K) in Figure 5-15 and Figure 5-16.
oscillation clock (B)
Setting Flag of SFR Register
2. FSEL = 1 when f
(Setting sequence of SFR registers)
(see CHAPTER 28 ELECTRICAL SPECIFICATIONS).
Set the oscillation stabilization time of OSTS as follows.
If a divided clock is selected and f
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by OSTS
Setting Flag of SFR Register
Table 5-5. CPU Clock Transition and SFR Register Setting Examples (5/6)
X
X
CLK
Register
> 10 MHz
Note 1
Note 1
Note 1
OSTS
CHAPTER 5 CLOCK GENERATOR
Unnecessary if the CPU is operating with
User’s Manual U19678EJ1V1UD
the high-speed system clock
CLK
Register
MSTOP
CSC
≤ 10 MHz, use with FSEL = 0 is possible even if f
SELDSC
0
0
0
0
Register
OSMC
FSEL
1
0/1
Note 2
0
DSCCTL Register
DSPO
Must not be
Register
checked
checked
checked
OSTC
Must be
Must be
0
Unnecessary
registers are
already set
if these
MCM0
1
1
1
DSCON
Register
X
CKC
> 10 MHz.
0
CSS
0
0
0