UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 584

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Cautions 1. When rewriting FR2 to FR0, LV1, and LV0 to other than the same data, stop A/D conversion once
Remark f
582
FR2
A/D Converter Mode Register (ADM)
0
0
0
0
1
1
1
1
×
×
0
0
0
0
1
1
1
1
FR1
2. The above conversion time does not include clock frequency errors. Select conversion time,
0
0
1
1
0
0
1
1
×
×
0
0
1
1
0
0
1
1
CLK
: CPU/peripheral hardware clock frequency
(ADCS = 0) beforehand.
taking clock frequency errors into consideration.
FR0
Sampling
0
1
0
1
0
1
0
1
×
×
0
1
0
1
0
1
0
1
INTAD
ADCS
timing
Figure 12-5. A/D Converter Sampling and A/D Conversion Timing
LV1
0
0
1
1
ADCS
LV0
Table 12-2. A/D Conversion Time Selection (2/2)
0
1
0
1
←
1 or ADS rewrite
Standard
speed 1
speed 2
Voltage
clear
SAR
Mode
boost
High
High
CHAPTER 12 A/D CONVERTER
User’s Manual U19678EJ1V1UD
(2) 2.7 V ≤ AV
Sampling
Setting prohibited
52.0
35.0
26.5
18.0
9.5
Setting prohibited
Setting prohibited
Setting prohibited
52.0
35.0
26.5
18.0
9.5
f
CLK
μ
μ
= 2 MHz
μ
μ
μ
μ
s
μ
μ
μ
μ
s
Conversion time
s
s
s
s
s
s
s
s
Successive conversion
REF
Setting prohibited 34.2
34.4
27.6
20.8
14.0
10.6
Setting prohibited
Setting prohibited 34.2
34.4
27.6
20.8
14.0
10.6
7.2
3.8
f
≤ 5.5 V
Conversion Time Selection
CLK
μ
μ
= 5 MHz
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
s
s
s
s
s
s
s
s
s
s
s
s
generation
to ADCR,
Transfer
INTAD
17.2
13.8
10.4
Setting prohibited
17.2
13.8
10.4
7.0
5.3
3.6
Setting prohibited
f
CLK
SAR
clear
μ
μ
μ
= 10 MHz
μ
μ
μ
μ
μ
μ
μ
μ
s
s
s
s
s
s
s
s
s
s
s
Conversion time
Sampling
17.1
8.6
Setting prohibited
17.1
8.6
6.9
5.2
3.5
Setting prohibited
f
CLK
μ
μ
μ
μ
μ
= 20 MHz
μ
μ
s
s
s
s
s
s
s
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
Conversion
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Clock (f
/20
/10
/8
/6
/4
/3
/2
/20
/10
/8
/6
/4
/3
/2
−
−
AD
)