UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 128

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Address
F003CH Pull-up resistor option register 12
F003EH Pull-up resistor option register 14
F00E0H Multiplication/division data register C (L) MDCL
F00E2H Multiplication/division data register C (H) MDCH
F00E8H Multiplication/division control
F00FEH BCD adjust result register
F0017H
F0030H
F0031H
F0033H
F0034H
F0035H
F0037H
F0043H
F0047H
F0048H
F0053H
F0057H
F0060H
F0061H
F0062H
F00F0H Peripheral enable register 0
F00F1H Peripheral enable register 1
F00F2H Peripheral enable register 2
F00F3H Operation speed mode control
F00F4H Regulator mode control register
F00F6H 40 MHz internal high-speed
F0100H
F0101H
F0102H
F0103H
F0104H
F0105H
126
A/D port configuration register
Pull-up resistor option register 0
Pull-up resistor option register 1
Pull-up resistor option register 3
Pull-up resistor option register 4
Pull-up resistor option register 5
Pull-up resistor option register 7
Port input mode register 3
Port input mode register 7
Port input mode register 8
Port output mode register 3
Port output mode register 7
Noise filter enable register 0
Noise filter enable register 1
Noise filter enable register 2
register
register
oscillation control register
Serial status register 00
Serial status register 01
Serial status register 02
Special Function Register (SFR)
Name
Table 3-6. Extended SFR (2nd SFR) List (1/6)
ADPC
PU0
PU1
PU3
PU4
PU5
PU7
PU12
PU14
PIM3
PIM7
PIM8
POM3
POM7
NFEN0
NFEN1
NFEN2
MDUC
PER0
PER1
PER2
OSMC
RMC
DSCCTL
BCDADJ
SSR00L
SSR01L
SSR02L
CHAPTER 3 CPU ARCHITECTURE
−
−
−
Symbol
User’s Manual U19678EJ1V1UD
SSR00
SSR01
SSR02
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
Manipulable Bit Range
1-bit
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
√
√
√
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−
−
√
−
−
−
−
−
−
−
8-bit
√
√
√
√
√
√
√
√
√
√
√
√
√
√
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−
−
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−
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−
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−
√
−
16-bit
−
−
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−
−
−
−
−
−
−
−
−
−
−
−
−
−
√
√
−
−
−
−
−
−
−
−
√
√
√
0000H
0000H
0000H
0000H
0000H
Reset
After
10H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
√
−
√
√
√
√
−
√
−
√
−
√
√
−
√
√
√
√
√
√
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√
√
√
√
√
√
√
√
√
√
−
√
√
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√
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√
−
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−
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−
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√
√
√
√
√
√
√
−
√
√
√
√
√
√
−
√
√
√
√
√
√
√
√
√
√
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√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
√
√
√
√
√
√
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√
√
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√
√
√
√
√
√
√
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√
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√
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√
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√
√
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√
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√