UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 598

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

596
The setting methods are described below.
<Change the channel>
<Complete A/D conversion>
<1> Set bit 5 (ADCEN) of peripheral enable register 0 (PER0) to 1.
<2> Select the conversion time by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of ADM, and select the
<3> Set bit 0 (ADCE) of A/D converter mode register (ADM) to 1.
<4> Set the channel to be used in the analog input mode by using bits 4 to 0 (ADPC4 to ADPC0) of the A/D
<5> Set the programmable gain amplifier operation to set the programmable gain amplifier output signal from
<6> Select a channel to be used by using bits 6 and 3 to 0 (ADOAS, ADS3 to ADS0) of the analog input
<7> Use bits 0 and 7 (ADTRS, ADTMD) of A/D converter mode register 1 (ADM1) to set the trigger mode.
<8> Set bit 7 (ADCS) of ADM to 1 to start A/D conversion.
<9> When one A/D conversion has been completed, an interrupt request signal (INTAD) is generated.
<10> Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH).
<11> Change the channel using bits 6 and 3 to 0 (ADOAS, ADS3 to ADS0) of ADS to start A/D conversion.
<12> When one A/D conversion has been completed, an interrupt request signal (INTAD) is generated.
<13> Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH).
<14> Clear ADCS to 0.
<15> Clear ADCE to 0.
<16> Clear bit 5 (ADCEN) of peripheral enable register 0 (PER0) to 0.
Cautions 1. Make sure the period of <3> to <8> is 1
operation mode by using bit 6 (ADMD) of ADM.
port configuration register (ADPC), bits 7 to 0 (PM27 to PM20) of port mode register 2 (PM2), bit 0
(PM80) of port mode register 8 (PM8), and bits 3 to 0 (PM153 to PM150) of port mode register 15
(PM15).
PGAI pin (PGAO) for the analog input channel (refer to 8.4.1 Starting comparator and programmable
gain amplifier operation).
channel specification register (ADS).
2. <3> may be done between <4> and <6>.
3. <3> can be omitted. However, ignore data of the first conversion after <8> in this case.
4. The period from <9> to <12> differs from the conversion time set using bits 5 to 1 (FR2 to
FR0, LV1, LV0) of ADM. The period from <11> to <12> is the conversion time set using
FR2 to FR0, LV1, and LV0.
CHAPTER 12 A/D CONVERTER
User’s Manual U19678EJ1V1UD
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s or more.