UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 876

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Notes 1.
874
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
2.
3. Do not use UART0 and CSI00 at the same time because they share flags for the interrupt request sources.
4. Do not use UART0 and CSI01 at the same time because they share flags for the interrupt request sources.
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
Do not use INTP3 and INTTMOFF0 at the same time because they share flags for the interrupt request
sources. If one of the interrupt sources INTP3 and INTTMOFF0 is generated, bit 5 of IF0L is set to 1. Bit
5 of MK0L, PR00L, and PR10L supports these two interrupt sources.
The INTP3 pin is shared with the TMOFF0 pin. Therefore, when using the TMOFF0 pin, select the valid
edges of INTP3 according to the valid edges of the TMOFF0 pin. (For details about selecting the valid
edges of the INTP3 pin, see 17.3 (4) External interrupt rising edge enable register 0 (EGP0), external
interrupt falling edge enable register 0 (EGN0). For details about selecting the valid edges of the
TMOFF0 pin, see 7.3 (19) TAU option mode register (OPMR). ). Also, when using INTP3, be sure to
disable edge detection of the TMOFF0 input (by setting the HIE0 bit of the OPCR register to 0).
If one of the interrupt sources INST0 and INTCSI00 is generated, bit 5 of IF0H is set to 1. Bit 5 of MK0H,
PR00H, and PR10H supports these two interrupt sources.
If one of the interrupt sources INSR0 and INTCSI01 is generated, bit 6 of IF0H is set to 1. Bit 6 of MK0H,
PR00H, and PR10H supports these two interrupt sources.
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
Table 17-2. Flags Corresponding to Interrupt Request Sources (1/3)
INTWDTI
INTLVI
INTP0
INTP1
INTP2
INTP3
INTTMOFF0
Note 1, 2
INTP4
INTP5
INTTMAD
INTCMP0
INTCMP1
INTDMA0
INTDMA1
INTST0
INTCSI00
INTSR0
INTCSI01
INTSRE0
Interrupt
Request
Flag
Note 1, 2
Note 3
Note 4
Note 3
Note 4
STIF0
CSIIF00
WDTIIF
LVIIF
PIF0
PIF1
PIF2
PIF3
TMOFFIF0
Note 1, 2
PIF4
PIF5
TMADIF
CMPIF0
CMPIF1
DMAIF0
DMAIF1
SRIF0
CSIIF01
SREIF0
CHAPTER 17 INTERRUPT FUNCTIONS
Interrupt Mask Flag
Note 1, 2
Note 3
Note 4
Note 3
Note 4
User’s Manual U19678EJ1V1UD
IF0L
IF0H
Register
WDTIMK
LVIMK
PMK0
PMK1
PMK2
PMK3
TMOFFMK0
Note 1, 2
PMK4
PMK5
TMADMK
CMPMK0
CMPMK1
DMAMK0
DMAMK1
STMK0
CSIMK00
SRMK0
CSIMK01
SREMK0
Priority Specification
Note 1, 2
Note 4
Note 3
Note 3
Note 4
Flag
MK0L
MK0H
Register
WDTIPR0, WDTIPR1
LVIPR0, LVIPR1
PPR00, PPR10
PPR01, PPR11
PPR02, PPR12
PPR03, PPR13
TMOFFPR00,
TMOFFPR10
PPR04, PPR14
PPR05, PPR15
TMADPR0,
TMADPR1
CMPPR00,
CMPPR10
CMPPR01,
CMPPR11
DMAPR00, DMAPR10
DMAPR01, DMAPR11
STPR00, STPR10
CSIPR000, CSIPR100
SRPR00, SRPR10
CSIPR001, CSIPR101
SREPR00, SREPR10
Interrupt Request Flag
Note 1, 2
Note 1, 2
Note 4
Note 3
Note 3
Note 4
PR00L,
PR10L
PR00H,
PR10H
Register