UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 913

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

is generated.
circuit voltage detection or execution of illegal instruction
Tables 19-1 and 19-2. Each pin is high impedance during reset signal generation or during the oscillation stabilization
time just after a reset release, except for P140
level is input to the RESET pin and program execution is started with the internal high-speed oscillation clock after
reset processing. A reset by the watchdog timer is automatically released, and program execution starts using the
internal high-speed oscillation clock (see Figures 19-2 to 19-4) after reset processing. Reset by POC and LVI circuit
power supply detection is automatically released when V
execution starts using the internal high-speed oscillation clock (see CHAPTER 20 POWER-ON-CLEAR CIRCUIT
and CHAPTER 21 LOW-VOLTAGE DETECTOR) after reset processing.
The following five operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit
(4) Internal reset by comparison of supply voltage of the low-voltage detector (LVI) or input voltage (EXLVI) from
(5) Internal reset by execution of illegal instruction
(6) Internal reset by a reset processing check error
External and internal resets start program execution from the address at 0000H and 0001H when the reset signal
A reset is effected when a low level is input to the RESET pin, the watchdog timer overflows, or by POC and LVI
When a low level is input to the RESET pin, the device is reset. It is released from the reset status when a high
Notes 1.
Cautions 1. For an external reset, input a low level for 10
Remark V
external input pin, and detection voltage
2.
2. During reset input, the X1 clock, XT1 clock (in the products other than the 78K0R/IB3), internal
3. When the STOP mode is released by a reset, the RAM contents in the STOP mode are held
4. When reset is effected, port pin P140 is set to low-level output and other port pins become
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
48-pin products of 78K0R/IC3, 78K0R/ID3 and 78K0R/IE3 only.
POR
(To perform an external reset upon power application, a low level of at least 10
continued during the period in which the supply voltage is within the operating range (V
2.7 V).)
high-speed oscillation clock, and internal low-speed oscillation clock stop oscillating.
External main system clock input becomes invalid.
during reset input.
high-impedance, because each SFR and 2nd SFR are initialized.
: POC power supply rise detection voltage
CHAPTER 19 RESET FUNCTION
User’s Manual U19678EJ1V1UD
Note 2
, which is low-level output.
Note 1
Note 1
DD
, and each item of hardware is set to the status shown in
≥ V
μ
s or more to the RESET pin.
POR
or V
DD
≥ V
LVI
after the reset, and program
μ
s must be
DD
911
≥