UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 622

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

620
Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01),
(5) Higher 7 bits of the serial data register 0n (SDR0n)
Symbol
SDR0n
Cautions 1. Be sure to clear bit 8 to “0”.
The lower 8 bits of the SDR0n register function as a transmit/receive buffer register. During reception, the
parallel data converted by the shift register is stored in the lower 8 bits, and during transmission, the data to be
transmitted to the shift register is set to the lower 8 bits.
SDR0n register can be read or written in 16-bit units.
However, the higher 7 bits can be written or read only when the operation is stopped (SE0n = 0). During
operation (SE0n = 1), a value is written only to the lower 8 bits of SDR0n register. When SDR0n register is
read during operation, 0 is always read.
Reset signal generation clears SDR0n register to 0000H.
Remarks 1. For the function of the lower 8 bits of SDR0n register, see 13.2 Configuration of Serial Array
SDR0n register is the transmit/receive data register (16 bits) of channel n.
transmit/receive buffer register, and bits 15 to 9 are used as a register that sets the division ratio of the
operation clock (f
If the CCS0n bit of serial mode register 0n (SMR0n) is cleared to 0, the clock set by dividing the operating
clock by the higher 7 bits of SDR0n register is used as the transfer clock.
FFF44H, FFF45H (SDR02), FFF46H, FFF47H (SDR03)
15
0
0
0
0
1
1
•
•
•
2. Setting SDR0n[15:9] = (0000000B, 0000001B) is prohibited when UART is used.
3. Setting SDR0n[15:9] = 0000000B is prohibited when simplified I
4. Do not write eight bits to the lower eight bits if operation is stopped (SEmn = 0). (If these
2. n: Channel number (n = 0 to 3)
SDR0n[15:9] to 0000001B or greater.
bits are written to, the higher seven bits are cleared to 0.)
Unit.
14
0
0
0
0
1
1
•
•
•
MCK
).
13
0
0
0
0
1
1
•
•
•
Figure 13-8. Format of Serial Data Register 0n (SDR0n)
SDR0n[15:9]
FFF11H (SDR00)
12
0
0
0
0
1
1
•
•
•
CHAPTER 13 SERIAL ARRAY UNIT
11
0
0
0
0
1
1
•
•
•
User’s Manual U19678EJ1V1UD
10
0
0
1
1
1
1
•
•
•
9
0
1
0
1
0
1
•
•
•
8
0
Transfer clock setting by dividing the operating clock (f
After reset: 0000H
7
6
5
R/W
FFF10H (SDR00)
f
f
MCK
MCK
f
f
f
f
MCK
MCK
MCK
MCK
4
•
•
•
/254
/256
/2
/4
/6
/8
Bits 7 to 0 function as a
3
2
C is used. Set
2
1
MCK
)
0