UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 765

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.2 Configuration of Serial Interface IICA
Serial interface IICA includes the following hardware.
(1) IICA shift register (IICA)
(2) Slave address register (SVA)
IICA is used to convert 8-bit serial data to 8-bit parallel data and vice versa in synchronization with the serial
clock. IICA can be used for both transmission and reception.
The actual transmit and receive operations can be controlled by writing and reading operations to IICA.
Cancel the wait state and start data transfer by writing data to IICA during the wait period.
IICA can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears IICA to 00H.
Cautions 1. Do not write data to IICA during data transfer.
This register stores local addresses when in slave mode.
SVA can be set by an 8-bit memory manipulation instruction.
However, rewriting to this register is prohibited while STD = 1 (while the start condition is detected).
Reset signal generation clears SVA to 00H.
Note Bit 0 is fixed to 0.
Address: FFF50H
Address: F0234H
Symbol
Symbol
SVA
IICA
2. Write or read IICA only during the wait period. Accessing IICA in a communication state
3. When communication is reserved, write data to IICA after the interrupt triggered by a stop
Registers
Control registers
other than during the wait period is prohibited. When the device serves as the master,
however, IICA can be written only once after the communication trigger bit (STT) is set to
1.
condition is detected.
Item
7
7
Figure 14-4. Format of Slave Address Register (SVA)
Table 14-1. Configuration of Serial Interface IICA
Figure 14-3. Format of IICA Shift Register (IICA)
After reset: 00H
After reset: 00H
CHAPTER 14 SERIAL INTERFACE IICA
6
6
IICA shift register (IICA)
Slave address register (SVA)
Peripheral enable register 0 (PER0)
IICA control register 0 (IICCTL0)
IICA status register (IICS)
IICA flag register (IICF)
IICA control register 1 (IICCTL1)
IICA low-level width setting register (IICWL)
IICA high-level width setting register (IICWH)
Port mode register 6 (PM6)
Port register 6 (P6)
User’s Manual U19678EJ1V1UD
5
5
R/W
R/W
4
4
Configuration
3
3
2
2
1
1
0
Note
0
0
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