UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 333

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.7.4 Operation as input pulse interval measurement
in synchronization with the count clock.
and, at the same time, the TCRn register is cleared to 0000H, and the INTTMn is output. If the counter overflows at
this time, the OVF bit of the TSRn register is set to 1. If the counter does not overflow, the OVF bit is cleared. After
that, the above operation is repeated.
depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the
captured value can be checked.
bit of the TSRn register is set to 1.
more overflows occur.
trigger.
Operation clock
The count value can be captured at the TIn valid edge and the interval of the pulse input to TIn can be measured.
The pulse interval can be calculated by the following expression.
TCRn operates as an up counter in the capture mode.
When the channel start trigger (TS0n) of timer channel start register (TS0) is set to 1, TCRn counts up from 0000H
When the TIn pin input valid edge is detected, the count value of TCRn register is transferred (captured) to TDRn
At the same time that the count value is captured to the TDRn register, the OVF bit of the TSRn register is updated
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF
Set STSn2 to STSn0 of the TMRn register to 001B to use the valid edges of TIn as a start trigger and a capture
When TEn = 1, a software operation (TSn = 1) can be used as a capture trigger, instead of using the TI0n pin input.
Note The operation clocks of channels 0 to 7 are selected from CK00 and CK01, and those of channels 8 to
Remark
TIn input pulse interval = Period of count clock × ((10000H × TSRn: OVF) + (Capture value of TDRn + 1))
Caution The TIn pin input is sampled using the operating clock selected with the CKSn bit of the
Note
11 from CK02 and CK03.
Figure 6-48. Block Diagram of Operation as Input Pulse Interval Measurement
TMRn register, so an error of up to one operating clock cycle occurs.
n = 00 to 11 (78K0R/IB3: n = 02 to 07 and 09)
CK00 or CK02
CK01 or CK03
TIn pin
TSn
detection
Edge
However, a normal interval value cannot be measured for the OVF bit, if two or
CHAPTER 6 TIMER ARRAY UNIT TAUS
User’s Manual U19678EJ1V1UD
Timer Data register n
register n (TCRn)
Timer counter
(TDRn)
controller
Interrupt
Interrupt signal
(INTTMn)
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