UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 792

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.5.9 Address match detection method
address.
address has been set to the slave address register (SVA) and when the address set to SVA matches the slave
address sent by the master device, or when an extension code has been received.
14.5.10 Error detection
register (IICA) of the transmitting device, so the IICA data prior to transmission can be compared with the transmitted
IICA data to enable detection of transmission errors. A transmission error is judged as having occurred when the
compared data values do not match.
14.5.11 Extension code
790
In I
Address match can be detected automatically by hardware. An interrupt request (INTIICA) occurs when a local
In I
(1) When the higher 4 bits of the receive address are either “0000” or “1111”, the extension code reception flag
(2) If “11110××0” is set to SVA by a 10-bit address transfer and “11110××0” is transferred from the master device,
(3) Since the processing after the interrupt request occurs differs according to the data that follows the extension
2
2
C bus mode, the master device can select a particular slave device by transmitting the corresponding slave
C bus mode, the status of the serial data bus (SDA0) during data transmission is captured by the IICA shift
(EXC) is set to 1 for extension code reception and an interrupt request (INTIICA) is issued at the falling edge of
the eighth clock. The local address stored in the slave address register (SVA) is not affected.
the results are as follows. Note that INTIICA occurs at the falling edge of the eighth clock.
• Higher four bits of data match: EXC = 1
• Seven bits of data match:
Remark
code, such processing is performed by software.
If the extension code is received while a slave device is operating, then the slave device is participating in
communication even if its address does not match.
For example, after the extension code is received, if you do not wish to operate the target device as a slave
device, set bit 6 (LREL) of the IICA control register 0 (IICCTL0) to 1 to set the standby mode for the next
communication operation.
Remark See the I
Slave Address
0 0 0 0 0 0 0
1 1 1 1 0 x x
1 1 1 1 0 x x
EXC:
COI:
other than those described above.
Bit 5 of IICA status register (IICS)
Bit 4 of IICA status register (IICS)
Table 14-3. Bit Definitions of Major Extension Codes
2
C bus specifications issued by NXP Semiconductors for details of extension codes
R/W Bit
CHAPTER 14 SERIAL INTERFACE IICA
0
0
1
COI = 1
User’s Manual U19678EJ1V1UD
General call address
10-bit slave address specification (during address
authentication)
10-bit slave address specification (after address match, when
read command is issued)
Description