UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 512

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remark
510
TAUS
default
setting
Channel
default
setting
Figure 7-99. Operation Procedure When Complementary Modulation Output Function Is Used (1/2)
p = 02, 04, 06
q = 03, 05, 07
Sets the TAU0EN and TAUOPEN bits of the PER2 register to 1. Power-on status. Each channel stops operating.
Sets the TPS0 register.
Sets the TMR00, TMR01, TMRp, and TMRq registers of eight
channels to be used (determines operation mode of
channels).
An interval (period) value is set to the TDR00 register of the
master channel, the number of interrupts to be thinned is set to
the TDR01 register of slave channel 1, a duty factor is set to the
TDRp register of slave channels 2, 4, 6, and a dead time width
is set to the TDRq register of slave channels 3, 5, 7.
Sets slave channel 1.
Sets slave channels 2 to 7.
Determines clock frequencies of CK00 and CK01.
Sets the TRC01 bit to 1 (trigger generation channel).
Sets the TOMp and TOMq bits to 1 (slave channel output
mode).
Sets the TOTp and TOTq bits to 1 (triangular wave PWM
output).
Sets the TOLp and TOLq bits to 0 (positive logic output).
Sets the TDEp and TDEq bits to 0 (stops dead time
control).
Sets the TREp and TREq bits to 1 (real-time output enable).
Real-time output level is set to the TROp and TROq bits.
Sets the TRCp and TRCq bits to 0 (non-trigger generation
channel).
Sets the TMEp and TMEq bits and determines the
modulated output control.
Sets the TO00, TOp, and TOq bits and determines default
level of the TOm output.
Sets the TOE00, TOEp, TOEq bits to 1 and enables
operation of TOm.
Clears the port register and port mode register to 0.
Software Operation
CHAPTER 7 INVERTER CONTROL FUNCTIONS
User’s Manual U19678EJ1V1UD
The TO00, TOp, and TOq default setting levels are
output when the port mode register is in output mode
and the port register is 0.
Power-off status
Channel stops operating.
(Clock is supplied and some power is consumed.)
The TO00, TOp, and TOq pins go into Hi-Z output
state.
TOp and TOq do not change because channel has
stopped operating.
The TO00, TOp, and TOq pins output the TOm set level.
(Clock supply is stopped and writing to each register
is disabled.)
(Clock supply is started and writing to each register
is enabled.)
Hardware Status