UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 355

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

values can be output.
the following expressions.
from the TOp pin. TCRp loads the value of TDRp, using INTTMn of the master channel as a start trigger, and starts
counting down. When TCRp = 0000H, TCRp outputs INTTMp and stops counting until the next start trigger (INTTMn
of the master channel) has been input. The output level of TOp becomes active one count clock after generation of
INTTMn from the master channel, and inactive when TCRp = 0000H.
the duty factor, and outputs a PWM waveform from the TOq pin. TCRq loads the value of TDRq, using INTTMn of the
master channel as a start trigger, and starts counting down. When TCRq = 0000H, TCRq outputs INTTMq and stops
counting until the next start trigger (INTTMn of the master channel) has been input. The output level of TOq becomes
active one count clock after generation of INTTMn from the master channel, and inactive when TCRq = 0000H.
same time.
6.8.3 Operation as multiple PWM output function
By extending the PWM function and using multiple slave channels, many PWM waveforms with different duty
For example, when using two slave channels, the period and duty factor of an output pulse can be calculated by
TCRn of the master channel operates in the interval timer mode and counts the periods.
TCRp of the slave channel 1 operates in one-count mode, counts the duty factor, and outputs a PWM waveform
In the same way as TCRp of the slave channel 1, TCRq of the slave channel 2 operates in one-count mode, counts
When channel 0 is used as the master channel as above, up to eleven types of PWM signals can be output at the
Caution To rewrite both TDRn of the master channel and TDRp of the slave channel 1, write access is
Remark
Remark
Pulse period = {Set value of TDRn (master) + 1} × Count clock period
Duty factor 1 [%] = {Set value of TDRp (slave 1)}/{Set value of TDRn (master) + 1} × 100
Duty factor 2 [%] = {Set value of TDRq (slave 2)}/{Set value of TDRn (master) + 1} × 100
necessary at least twice. Since the values of TDRn and TDRp are loaded to TCRn and TCRp after
INTTMn is generated from the master channel, if rewriting is performed separately before and
after generation of INTTMn from the master channel, the TOp pin cannot output the expected
waveform. To rewrite both TDRn of the master and TDRp of the slave, be sure to rewrite both the
registers immediately after INTTMn is generated from the master channel (This applies also to
TDRq of the slave channel 2).
n = 00, 02, 04, 06, 08, 10
n < p < q ≤ 11
However, p and q are consecutive integers.
Although the duty factor exceeds 100% if the set value of TDRp (slave 1) > {set value of TDRn
(master) + 1} or if the {set value of TDRq (slave 2)} > {set value of TDRn (master) + 1}, it is
summarized into 100% output.
CHAPTER 6 TIMER ARRAY UNIT TAUS
User’s Manual U19678EJ1V1UD
353