UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 254

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.6.3 Example of setting X1 oscillator
oscillation clock. To subsequently change the clock to the X1 oscillation clock, set the oscillator and start oscillation by
using the operation speed mode control register (OSMC), clock operation mode control register (CMC), and clock
operation status control register (CSC) and wait for oscillation to stabilize by using the oscillation stabilization time
counter status register (OSTC). After the oscillation stabilizes, set the X1 oscillation clock to f
clock control register (CKC).
252
<7> Wait until the DSCS bit changes to 1.
<8> Use the MDIV2 to MDIV0 bits of the CKC register to specify the division ratio for the CPU/peripheral hardware
<4> Clear (0) the MSTOP bit of the CSC register to start oscillating the X1 oscillator.
After a reset release, the CPU/peripheral hardware clock (f
[Register settings] Set the register in the order of <1> to <7> below.
<1> Use the OSMC register to set the frequency of the CPU/peripheral hardware.
<2> Set (1) the FSEL bit and then wait for 10
<3> Set (1) the OSCSEL bit of the CMC register to operate the X1 oscillator.
Note
clock.
OSMC
CMC
CKC
CSC
CLS bit is not provided in the 78K0R/IB3. In the 78K0R/IB3, bit 7 is fixed to 0.
FSEL bit: Set this bit to 0 if the CPU/peripheral hardware clock is 10 MHz or less.
AMPH bit: Set this bit to 0 if the X1 oscillation clock is 10 MHz or less.
OSCSELS bit
Note
XTSTOP bit
Note
MSTOP
CLS
EXCLK
7
0
7
0
7
0
7
0
Note
OSCSELS bit is not provided in the 78K0R/IB3. In the 78K0R/IB3, bit 4 is fixed to 0.
XTSTOP bit is not mounted onto the 78K0R/IB3. In the 78K0R/IB3, bit 6 is fixed to 0.
Note
XTSTOP
Note
OSCSEL
: Set this bit to 0 to oscillate the XT1 oscillator.
CSS
: Set this bit to 1 to set P122 and P123 to XT1 oscillation mode.
6
0
6
0
6
1
6
1
Note
CHAPTER 5 CLOCK GENERATOR
MCS
User’s Manual U19678EJ1V1UD
0
0
0
0
5
5
5
5
μ
s.
OSCSELS
MCM0
4
0
4
0
4
0
4
0
CLK
Note
) always starts operating with the internal high-speed
3
1
3
0
3
0
3
0
MDIV2
0/1
2
2
0
2
0
2
0
MDIV1
0/1
CLK
1
1
0
1
0
1
0
by using the system
HIOSTOP
MDIV0
AMPH
FSEL
0/1
0
0
1
0
1
0
0