UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 258

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1) CPU operating with internal high-speed oscillation clock (B) after reset release (A)
(2) CPU operating with high-speed system clock (C) after reset release (A)
(3) CPU operating with subsystem clock (D) after reset release (A) (products other than 78K0R/IB3)
256
(A) → (B)
Status Transition
(A) → (B) → (D)
Status Transition
(A) → (B) → (C)
(X1 clock: 2 MHz ≤ f
(A) → (B) → (C)
(X1 clock: 10 MHz < f
(A) → (B) → (C)
(external main clock)
Table 5-5 shows transition of the CPU clock and examples of setting the SFR registers.
Notes 1. The CMC register can be written only once by an 8-bit memory manipulation instruction after reset
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set
Note The CMC register can be written only once by an 8-bit memory manipulation instruction after reset release.
Remark (A) to (K) in Table 5-5 correspond to (A) to (K) in Figure 5-15 and Figure 5-16, Figure.
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
2. FSEL = 1 when f
(Setting sequence of SFR registers)
(see CHAPTER 28 ELECTRICAL SPECIFICATIONS).
Status Transition
release.
If a divided clock is selected and f
Setting Flag of SFR Register
Table 5-5. CPU Clock Transition and SFR Register Setting Examples (1/6)
X
Setting Flag of SFR Register
X
≤ 10 MHz)
≤ 20 MHz)
CLK
> 10 MHz
CHAPTER 5 CLOCK GENERATOR
User’s Manual U19678EJ1V1UD
SFR registers doesn’t have to be set (default status after reset release).
EXCLK
CMC Register
CLK
0
0
1
OSCSELS
CMC Register
≤ 10 MHz, use with FSEL = 0 is possible even if f
1
OSCSEL
1
1
1
Note
Note 1
CSC Register
AMPH
XTSTOP
0/1
0
1
SFR Register Setting
0
Register
MSTOP
CSC
0
0
0
Stabilization
Waiting for
Necessary
Oscillation
Register
OSMC
0/1
FSEL
1
Note 2
0
Note 2
checked
checked
checked
Register
Must be
Must be
OSTC
not be
Must
X
CKC Register
> 10 MHz.
CSS
Register
MCM0
1
CKC
1
1
1