UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 267

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.6.8 Conditions before clock oscillation is stopped
conditions before the clock oscillation is stopped.
Note
Internal high-speed
oscillation clock
X1 clock
External main system clock
Subsystem clock
40 MHz internal high-speed
oscillation clock
Remarks 1. The number of clocks listed in Table 5-8 to Table 5-10 is the number of CPU clocks before switchover.
The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and
The 78K0R/IB3 doesn’t have the subsystem clock.
Clock
2. Calculate the number of clocks in Table 5-8 to Table 5-10 by removing the decimal portion.
(f
Set Value Before Switchover
(f
Table 5-11. Conditions Before the Clock Oscillation Is Stopped and Flag Settings
CLK
Note
CLK
Example When switching the main system clock from the internal high-speed oscillation clock to the
= f
0
1
= f
MAIN
SUB
Table 5-10. Maximum Number of Clocks Required for f
)
)
CSS
high-speed system clock (@ oscillation with f
MCS = 1 or CLS = 1
(The CPU is operating on a clock other than the internal high-speed
oscillation clock.)
MCS = 0 or CLS = 1
(The CPU is operating on a clock other than the high-speed system clock.)
CLS = 0
(The CPU is operating on a clock other than the subsystem clock.)
SELDSC = 0, DSPO = 0
(The main system clock is operating on a clock other than the 40 MHz
internal high-speed oscillation clock.)
1 + f
f
f
f
f
MAIN
MAIN
MAIN
MAIN
IH
<f
>f
<f
>f
/f
SUB
SUB
SUB
SUB
MX
= 1 + 8/10 = 1 + 0.8 = 1.8 → 2 clocks
Conditions Before Clock Oscillation Is Stopped
CHAPTER 5 CLOCK GENERATOR
1 + 2f
2 + f
User’s Manual U19678EJ1V1UD
SUB
(External Clock Input Disabled)
SUB
/f
/f
MAIN
MAIN
(f
CLK
clock
clock
= f
0
MAIN
Set Value After Switchover
)
IH
CSS
= 8 MHz, f
2 + f
1 + 2f
MAIN
MAIN
/f
MAIN
SUB
/f
MX
SUB
(f
CLK
clock
↔ f
= 10 MHz)
clock
1
= f
SUB
SUB
)
HIOSTOP = 1
MSTOP = 1
XTSTOP = 1
DSCON = 0
Flag Settings of SFR
Register
265