UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 433

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.5.7 Interrupt signal thinning function
master channel being thinned by the specified number of times from the slave channel.
triangular wave PWM output function. The setting of the master channel is therefore the same as in 7.5.6
Operation as 6-phase triangular wave PWM output function. The number of interrupts to be thinned can be
calculated by the following expression.
and TOn is not toggled when MDn0 of TMRn is 0. INTTMn is output and TOn is toggled when MDn0 of TMRn is 1.
Afterward, TCRn counts down along with the count clock. When TCRn has become 0000H, INTTMn is output and
TOn is toggled upon the next count clock. TCRn loads the value of TDRn again at the same timing. Similar operation
is continued hereafter.
signals of the master channel.
outputs INTTMm when TCRm becomes 0000H. Similar operation is continued hereafter.
events.
The interrupt signal thinning function uses two channels in combination to output INTTMm that is INTTMn of the
It assumes the slave channel to be used as a sub-function of the function described in 7.5.6 Operation as 6-phase
TCRn of the master channel counts down in the interval timer mode.
TCRn loads the value of TDRn by setting the channel start trigger bit (TSn) to 1. At this time, INTTMn is not output
The slave channel operates as a down counter in the event counter mode and controls the thinning of INTTMn
TCRm loads the value of TDRm by setting the channel start trigger bit (TSm) to 1.
TCRm counts down along with the INTTMn output of the master channel, and loads the value of TDRm again and
TOn and TOm cannot be used, because TOn and TOm becomes an irregular waveform that depends on external
TDRn of the master channel becomes valid from the next start timing (master channel INTTMn generation).
TDRm of the slave channel becomes valid from the next start timing (slave channel INTTMm generation).
Remark n = 00
Number of interrupts to be thinned = Set value of TDRm (slave channel)
→ Outputting INTTMn of the master channel from INTTMm of the slave channel every {Set value of TDRm
(slave) + 1} times
m = 01
CHAPTER 7 INVERTER CONTROL FUNCTIONS
User’s Manual U19678EJ1V1UD
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