UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 880

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UPD78F1233GB-GAH-AX

Manufacturer Part Number
UPD78F1233GB-GAH-AX
Description
MCU 16BIT 78K0R/LX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet

Specifications of UPD78F1233GB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1233GB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(Note and Caution are listed on the next page.)
878
(1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H)
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is
executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or
upon reset signal generation.
When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt
routine is entered.
IF0L, IF0H, IF1L, IF1H, IF2L, and IF2H can be set by a 1-bit or 8-bit memory manipulation instruction. When
IF0L and IF0H, IF1L and IF1H, and IF2L and IF2H are combined to form 16-bit registers IF0, IF1, and IF2, they
can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Address: FFFE0H After reset: 00H R/W
Address: FFFE1H
Address: FFFE2H
Address: FFFE3H
Address: FFFD0H
Symbol
Symbol
Symbol
Symbol
Symbol
Figure 17-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) (1/2)
IF0H
IF1H
IF0L
IF1L
IF2L
increases by 2 clocks.
SREIF0
TMIF03
TMIF04
TMIF08
PIF5
<7>
<7>
<7>
<7>
<7>
After reset: 00H
After reset: 00H
After reset: 00H
After reset: 00H
CSIIF01
TMVIF1
TMIF02
SRIF0
MDIF
PIF4
<6>
<6>
<6>
<6>
<6>
Note 1
CHAPTER 17 INTERRUPT FUNCTIONS
R/W
CSIIF00
R/W
R/W
R/W
TMOFFIF0
TMMIF1
TMVIF0
TMIF01
STIF0
PIF3
<5>
<5>
<5>
<5>
<5>
User’s Manual U19678EJ1V1UD
Note 1
TMOFFIF1
PIF7
DMAIF1
TMMIF0
TMIF00
PIF2
<4>
<4>
<4>
<4>
<4>
Note 3
Note 3
IICAIF
PIF6
DMAIF0
PIF1
<3>
<3>
<3>
<3>
3
0
Note 3
Note 2
RTCIIF
CMPIF1
SREIF1
TMIF07
PIF0
<2>
<2>
<2>
<2>
<2>
Note 3
RTCIF
CMPIF0
TMIF06
SRIF1
LVIIF
<1>
<1>
<1>
<1>
<1>
Note 3
TMADIF
CSIIF10
WDTIIF
TMIF05
IICIF10
STIF1
ADIF
<0>
<0>
<0>
<0>
<0>

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