UPD78F1233GB-GAH-AX Renesas Electronics America, UPD78F1233GB-GAH-AX Datasheet - Page 425

• Manufacturer Part Number: UPD78F1233GB-GAH-AX
• Description: MCU 16BIT 78K0R/LX3 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1233GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

value of TDRp at the first count clock, after the channel start trigger bit (TSp) is set to 1. Hereafter, counting up and
counting down is switched in accordance with the operation of the master channel. INTTMp is output when TCRp
becomes 0001H.
operation is continued hereafter.
as the start trigger. When TCRq becomes 0000H, it outputs INTTMq and stops counting until the next start trigger is
input (INTTMq of slave channels 3, 5, 7). INTTMq of slave channels 3, 5, 7 cannot be used, because the number of
times it occurs within the carrier cycle period cannot be specified (0 to 3 times).
(INTTMp, INTTMq) of slave channels 2, 4, 6 (duty) and slave channels 3, 5, 7 (dead time). A positive-phase
waveform and a reverse-phase waveform are output by controlling the TOLp and TOLq bits of the TOL0 registers of
slave channels 2, 4, 6 and slave channels 3, 5, 7.
setting TOLp and TOLq. When TOLp and TOLq are set to 0, a positive-phase waveform to which dead time has been
added on the positive logic side of the PWM duty is output. When TOLp and TOLq are set to 1, a reverse-phase
waveform to which dead time has been added on the inverted logic side of the PWM duty is output (TOLq = 1 when
TOLp = 0, and TOLq = 0 when TOLp = 1).
uses the generation of INTTMp while the TCRp register counts down as the start trigger. The reset condition of TOp
(TOLp = 0) is the generation of INTTMp of slave channels 2, 4, 6 while TCRp counts up.
condition of TOq (TOLq = 0) is the generation of INTTMq by the operation of slave channels 3, 5, 7, which uses the
generation of INTTMp while TCRp counts up as the start trigger.
6 and 3, 5, 7 by setting TOLp and TOLq.
TCRp of slave channels 2, 4, 6 operate in the up and down count mode, and counts the duty. TCRp loads the
TCRp loads the value of TDRp again when INTTM00 is generated in an up status of the master channel. Similar
TCRq of slave channels 3, 5, 7 operate in the one-count mode, and counts the dead time.
TCRq loads the value of TDRq and counts down by using count start timing and INTTMp of slave channels 2, 4, 6
A 6 triangular wave modulation PWM waveform is output by changing TOp and TOq by the count operations
It is also possible to specify whether to add dead time to the positive logic output or the inverted logic output by
Note that the active level of TOp and TOq can be changed by setting the TLS2 to TLS7 bits of the OPMR register.
The set condition of TOp (TOLp = 0) is the generation of INTTMq by the operation of slave channels 3, 5, 7, which
The set condition of TOq (TOLq = 1) is the generation of INTTMp while the TCRp register counts down. The reset
If the set conditions and reset conditions of TOp and TOq conflict, the set conditions take precedence.
The PWM waveform with dead time can be switched between positive and negative phases for slave channels 2, 4,
Cautions 1. TDR00 of the master channel must be rewritten during an up status period of slave channels
Remark p = 02, 04, 06
2. TS00, TSp, or TSq cannot be set to “1” (forcible restart) while TE00 = 1, TEp = 1, or TEq = 1. If
q = 03, 05, 07
TS00, TSp, or TSq is set to “1” while TE00 = 1, TEp = 1, or TEq = 1, the counter value (TCR00,
TCRp, or TCRq) will be illegal and TO00, TOp, or TOq will not be able to output the expected
waveform.
2, 4, 6 (The count status is judged by CSF (TSRp register) of the slave channel or the TO00
output level of the master channel). When the value of TDR00 is rewritten during a down
status period, the periods of the down status and up status differ and an expected waveform
cannot be output, because the value of TDRn of the rewritten master channel becomes valid
at the next period.
CHAPTER 7 INVERTER CONTROL FUNCTIONS
User’s Manual U19678EJ1V1UD
423